参数资料
型号: DP83848HSQ/NOPB
厂商: National Semiconductor
文件页数: 3/82页
文件大小: 0K
描述: IC TXRX ETHERNET PHYTER 40-LLP
产品培训模块: PHYTER® Family
标准包装: 1
类型: 收发器
驱动器/接收器数: 1/1
规程: 以太网
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-LLP-EP(6x6)
包装: 剪切带 (CT)
配用: DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H
其它名称: *DP83848HSQ/NOPB
DP83848HSQCT
www.national.com
10
DP
83
848
H
1.3 Clock Interface
RX_ER
S, O, PU
34
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK
to indicate that an invalid symbol has been detected within a re-
ceived packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Assert high synchronously to X1 when-
ever it detects a media error and RX_DV is asserted in 100 Mb/s
mode.
This pin is not required to be used by a MAC, in either MII or RMII
mode, since the Phy is required to corrupt data on a receive error.
RXD_0
RXD_1
RXD_2
RXD_3
S, O, PD
36
37
38
39
MII RECEIVE DATA: Nibble wide receive data signals driven syn-
chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz
for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driv-
en synchronously to the X1 clock, 50 MHz.
CRS/CRS_DV
S, O, PU
33
MII CARRIER SENSE: Asserted high to indicate the receive me-
dium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal
combines the RMII Carrier and Receive Data Valid indications.
For a detailed description of this signal, see the RMII Specifica-
tion.
COL
S, O, PU
35
MII COLLISION DETECT: Asserted high to indicate detection of
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this
pin is also asserted for a duration of approximately 1
s at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-
nal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL-
signal is required. The MAC will recover CRS from the CRS_DV
signal and use that along with its TX_EN signal to determine col-
lision.
Signal Name
Type
Pin #
Description
Signal Name
Type
Pin #
Description
X1
I
28
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock
reference input for the DP83848H and must be connected to a 25
MHz 0.005% (+50 ppm) clock source. The DP83848H supports
either an external crystal resonator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin
X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock refer-
ence input for the RMII mode and must be connected to a 50 MHz
0.005% (+50 ppm) CMOS-level oscillator source.
X2
O
27
CRYSTAL OUTPUT: This pin is the primary clock reference out-
put to connect to an external 25 MHz crystal resonator device.
This pin must be left unconnected if an external CMOS oscillator
clock source is used.
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