参数资料
型号: DP83848HSQ/NOPB
厂商: National Semiconductor
文件页数: 28/82页
文件大小: 0K
描述: IC TXRX ETHERNET PHYTER 40-LLP
产品培训模块: PHYTER® Family
标准包装: 1
类型: 收发器
驱动器/接收器数: 1/1
规程: 以太网
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-LLP-EP(6x6)
包装: 剪切带 (CT)
配用: DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H
其它名称: *DP83848HSQ/NOPB
DP83848HSQCT
33
www.national.com
DP
83
84
8
H
5.2 ESD Protection
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
need be implemented during the manufacturing process
to greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo-
nents are less sensitive from ESD events.
See Section 8.0 for ESD rating.
5.3 Clock In (X1) Recommendations
The DP83848H supports an external CMOS level oscilla-
tor source or a crystal resonator device.
Oscillator
If an external clock source is used, X1 should be tied to
the clock source and X2 should be left floating.
The CMOS oscillator specifications for MII Mode are listed
Mode, the CMOS oscillator specifications are listed in
it is not recommended that the system clock out, Pin 21,
be used as the reference clock to the MAC without first
verifying the interface timing. See AN-1405 for more
details.
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi-
cal connection for a crystal resonator circuit. The load
capacitor values will vary with the crystal vendors; check
with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 100
W
and a maximum of 500
W. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 33 pF, and R1 should be set at 0.
Specification for 25 MHz crystal are listed in Table 8.
Figure 12. Crystal Oscillator Circuit
X1
X2
CL2
CL1
R1
Table 7. 25 MHz Oscillator Specification
Parameter
Min
Typ
Max
Units
Condition
Frequency
50
MHz
Frequency
Tolerance
+50
ppm
Operational Tem-
perature
Frequency
Stability
+50
ppm
1 year aging
Rise / Fall Time
6
nsec
20% - 80%
Jitter
8001
psec
Short term
Jitter
8001
psec
Long term
Symmetry
40%
60%
Duty Cycle
1. This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to
AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,” for details on jitter performance.
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