参数资料
型号: DS1345YG-70-IND
厂商: Maxim Integrated Products, Inc.
英文描述: 1024k Nonvolatile SRAM with Battery Monitor
中文描述: 1024k非易失SRAM与电池监视器
文件页数: 8/12页
文件大小: 229K
代理商: DS1345YG-70-IND
DS1345Y/AB
8 of 12
POWER-DOWN/POWER-UP TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
V
CC
slew from V
TP
to 0V
t
F
V
CC
Fail Detect to
RST
Active
t
RPD
V
CC
slew from 0V to V
TP
t
R
V
CC
Valid to
CE
and
WE
Inactive
t
PU
V
CC
Valid to End of Write Protection
t
REC
V
CC
Valid to
RST
Inactive
t
RPU
V
CC
Valid to
BW
Valid
t
BPU
BATTERY WARNING TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
Battery Test Cycle
t
BTC
Battery Test Pulse Width
t
BTPW
Battery Test to
BW
Active
t
BW
(t
A
= 25
°
C)
PARAMETER
SYMBOL
Expected Data Retention Time
t
DR
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3. t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4. t
DS
is measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high-impedance state during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high-impedance state during this period.
8. If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high impedance state during this period.
MIN
150
150
150
TYP
200
MAX
1.5
15
2
125
350
1
UNITS NOTES
μ
s
μ
s
μ
s
μ
s
ms
ms
ms
s
11
14
14
14
MIN
TYP
24
MAX
1
1
UNITS NOTES
hr
s
s
MIN
10
TYP
MAX
UNITS NOTES
years
9
相关PDF资料
PDF描述
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