参数资料
型号: DS21448L+
厂商: Maxim Integrated Products
文件页数: 26/60页
文件大小: 0K
描述: IC LIU QUAD E1/T1/J1 128-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 4/4
规程: T1/E1/J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
产品目录页面: 1430 (CN2011-ZH PDF)
DS21448 3.3V T1/E1/J1 Quad Line Interface
32 of 60
Table 6-C. Definition of Received Errors
ERROR
E1 OR T1
DEFINITION OF RECEIVED ERRORS
BPV
E1/T1
Two consecutive marks with the same polarity. Ignores BPVs because of HDB3 and B8ZS zero
suppression when CCR2.3 = 0. Typically used with AMI coding (CCR2.3 = 1). ITU-T O.161.
CV
E1
When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two consecutive BPVs with the same
polarity. ITU-T O.161.
EXZ
E1
When four or more consecutive zeros are detected.
When receiving AMI-coded signals (CCR2.3 = 1), detection of 16 or more 0s or a BPV. ANSI T1.403
1999.
EXZ
T1
When receiving B8ZS-coded signals (CCR2.3 = 0), detection of eight or more 0s or a BPV. ANSI
T1.403 1999.
PRBS
E1/T1
A bit error in a received PRBS pattern. See Section 6.3 for details. ITU-T O.151.
Table 6-D. Function of ECRS Bits and RNEG Pin
E1 or T1
(CCR1.7)
ECRS2
(CCR6.2)
ECRS1
(CCR6.1)
ECRS0
(CCR6.0)
RHBE
(CCR2.3)
FUNCTION OF ECR COUNTERS/RNEG
(Note 1)
0
X
CVs
0
1
X
BPVs (HDB3 codewords not counted)
0
1
0
X
CVs + EXZs
0
1
X
BPVs + EXZs
1
0
X
0
BPVs (B8ZS codewords not counted)
1
0
X
1
0
BPVs + 8 EXZs
1
0
X
0
1
BPVs
1
0
X
1
BPVs + 16 EXZs
X
1
X
PRBS Errors (Note 2)
Note 1: RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).
Note 2: PRBS errors are always output at PBEO, independent of ECR control bits and NRZ mode, and are not present at RNEG.
6.5 Error Counter Update
A 0-to-1 transition of the ECUE (CCR1.4) control bit updates the ECR registers with the current values and resets
the counters. ECUE must be set back to 0 and another 0-to-1 transition must occur for subsequent reads/resets of
the ECR registers. Note that the DS21448 can report errors at RNEG when in NRZ mode (CCR1.6 = 1) by
outputting a pulse for each error occurrence. The counter saturates at 65,535 and does not roll over.
ECR1 (11H): Upper Error Count Register 1/ECR2 (12H): Lower Error Count Register 2
(MSB)
(LSB)
E15
E14
E13
E12
E11
E10
E9
E8
ECR1
E7
E6
E5
E4
E3
E2
E1
E0
ECR2
NAME
POSITION
FUNCTION
E15
ECR1.7
MSB of the 16-bit error count.
E0
ECR2.0
LSB of the 16-bit error count.
6.6 Error Insertion
When IBPV (CCR3.1) is transitioned from 0 to 1, the device waits for the next occurrence of three consecutive 1s
to insert a BPV. IBPV must be cleared and set again for another BPV error insertion. See Figure 1-3 for details on
the insertion of the BPV into the data stream.
When IBE (CCR3.0) is transitioned from 0 to 1, the device inserts a logic error. IBE must be cleared and set again
for another logic error insertion. See Figure 1-2 and Figure 1-3 for details about the logic error insertion into the
data steam.
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