DS21448L+ (Maxim) PDF资料下载 Datasheet(38/60 页)

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参数资料

型号：	DS21448L+
厂商：	Maxim Integrated Products
文件页数：	38/60页
文件大小：	0K
描述：	IC LIU QUAD E1/T1/J1 128-LQFP
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	72
类型：	线路接口装置（LIU）
驱动器/接收器数：	4/4
规程：	T1/E1/J1
电源电压：	3.135 V ~ 3.465 V
安装类型：	表面贴装
封装/外壳：	128-LQFP
供应商设备封装：	128-LQFP（14x20）
包装：	管件
产品目录页面：	1430 (CN2011-ZH PDF)

DS21448 3.3V T1/E1/J1 Quad Line Interface

43 of 60

8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT

The DS21448 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and

EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Table 8-A). The DS21448

contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port

(TAP) and Boundary Scan Architecture:

Test Access Port

TAP Controller

Instruction Register

Bypass Register

Boundary Scan Register

Device Identification Register

The TAP has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in

Section 1 for details. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE

1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.

Figure 8-1. JTAG Block Diagram

8.1 JTAG TAP Controller State Machine

This section covers the operation of the TAP controller state machine. See Figure 8-2 for details on each of the

states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the

rising edge of JTCLK (Table 8-B).

Test-Logic-Reset. Upon power-up, the TAP controller is in test-logic-reset state. The instruction register contains

the IDCODE instruction. All system logic of the device operates normally.

Run-Test-Idle. The run-test-idle is used between scan operations or during specific tests. The instruction register

and test registers remain idle.

Select-DR-Scan. All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the

controller into the capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK

moves the controller to the select-IR-scan state.

JTDI

JTMS

JTCLK

JTRST

JTDO

TEST ACCESS PORT

CONTROLLER

VDD

BOUNDRY SCAN

BYPASS

INSTRUCTION

IDENTIFICATION

MUX

SELECT

OUTPUT ENABLE

10k

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