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| 型号： | DS21448L+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 40/60页 |
| 文件大小： | 0K |
| 描述： | IC LIU QUAD E1/T1/J1 128-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1/E1/J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-LQFP（14x20） |
| 包装： | 管件 |
| 产品目录页面： | 1430 (CN2011-ZH PDF) |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
45 of 60
Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this
state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and initiates a scan
sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the
test-logic-reset state.
Capture-IR. The capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the
exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the shift-IR state.
Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK toward the serial output. The parallel register and all test registers
remain at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the exit1-IR state.
A rising edge on JTCLK with JTMS LOW keeps the controller in the shift-IR state while moving data one stage
through the instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS LOW puts the controller in the pause-IR state. If JTMS is HIGH on the
rising edge of JTCLK, the controller enters the update-IR state and terminates the scanning process.
Pause-IR. Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK
puts the controller in the exit2-IR state. The controller remains in the pause-IR state if JTMS is LOW during a rising
edge on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS HIGH puts the controller in the update-IR state. The controller loops
back to shift-IR if JTMS is LOW during a rising edge of JTCLK in this state.
Update-IR. The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current
instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the run-test-idle state. With JTMS HIGH,
the controller enters the select-DR-scan state.
8.2 Instruction Register
The instruction register contains a shift register, as well as a latched parallel output, and is 3 bits in length. When
the TAP controller enters the shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage toward the serial
output at JTDO. A rising edge on JTCLK in the exit1-IR state or the exit2-IR state with JTMS HIGH moves the
controller to the update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift
register to the instruction parallel output. Table 8-A shows the instructions supported by the DS21448 and its
respective operational binary codes.
Table 8-A. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD. This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions.
The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into
the boundary scan register through JTDI using the shift-DR state.
BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s
normal operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21448L+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448L+W | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448LDK | 功能描述:KIT DESIGN LIU DS21448L T1/J1/E1 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS21448LN | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448LN+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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