参数资料
型号: DS21FF42N+
厂商: Maxim Integrated Products
文件页数: 111/114页
文件大小: 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 300mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 300-BBGA
供应商设备封装: 300-PBGA(27x27)
包装: 管件
DS21FT42/DS21FF42
96 of 114
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING
(with elastic store enabled) Figure 23-5
RECEIVE SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 23-6
RSER
LSB MSB
LSB
CHANNEL 1
RCHCLK
RCHBLK
RSYSCLK
RSYNC
CHANNEL 31
CHANNEL 32
1
3
4
Notes:
1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one
2. RSYNC is in the output mode (RCR2.3 = 0)
3. RSYNC is in the input mode (RCR2.3 = 1)
4. RCHBLK is forced to one in the same channels as RSER (see Note 1)
5. The F-Bit position is passed through the receive side elastic store and occupies the MSB position of
channel 1.
RSYNC
2
RMSYNC
RSIG
D/B
CHANNEL 1
CHANNEL 31
CHANNEL 32
A
B
C/A
A
BC/A
F5
RSER
LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIG
D/B
C/D
B
A
C/A
B
FRAMER 3, CHANNEL 32
A
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
D/B
C/D
B
A
FRAMER 1, CHANNEL 1
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR2.3 = 1).
3
RSER
RSYNC
RSIG
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
RSER
RSIG
FR2 CH32 FR3 CH32 FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
FR2 CH32 FR3 CH32 FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
1
2
BIT DETAIL
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