参数资料
型号: DS21FF42N+
厂商: Maxim Integrated Products
文件页数: 80/114页
文件大小: 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 300mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 300-BBGA
供应商设备封装: 300-PBGA(27x27)
包装: 管件
DS21FT42/DS21FF42
68 of 114
SYMBOL
POSITION
NAME AND DESCRIPTION
TFS
HCR.5
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR
HCR.4
Transmit HDLC/BOC Reset. A 0 to 1 transition will reset
both the HDLC controller and the transmit BOC circuitry.
Must be cleared and set again for a subsequent reset.
TABT
HCR.3
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set
again for a subsequent abort to be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a one just
before the last data byte of a HDLC packet is written into the
transmit FIFO at THFR. The HDLC controller will clear this
bit when the last byte has been transmitted.
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
HSR: HDLC STATUS REGISTER (Address = 01 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
TMEN
D
SYMBOL
POSITION
NAME AND DESCRIPTION
RBOC
HSR.7
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to
a No Valid Code seen or vice versa. The setting of this bit
prompt the user to read the RBOC register for details.
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check
complete) or when the controller has experienced a message
fault such as a CRC checking error, or an overrun condition,
or an abort has been seen. The setting of this bit prompts the
user to read the RHIR register for details.
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller
detects an opening byte. The setting of this bit prompts the
user to read the RHIR register for details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64–byte
FIFO fills beyond the half way point. The setting of this bit
prompts the user to read the RHIR register for details.
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