参数资料
型号: DS21FF42N+
厂商: Maxim Integrated Products
文件页数: 114/114页
文件大小: 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 300mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 300-BBGA
供应商设备封装: 300-PBGA(27x27)
包装: 管件
DS21FT42/DS21FF42
99 of 114
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING
(with elastic store enabled) Figure 23-11
TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING
(with elastic store enabled) Figure 23-12
TSER
LSB MSB
F
MSB
CHANNEL 23
CHANNEL 24
LSB
CHANNEL 1
TCHCLK
TCHBLK
TSYSCLK
TSSYNC
1
Notes:
1. TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at
TSIG will be ignored during channel 24).
TSIG
A
CHANNEL 23
CHANNEL 24
D/B
CHANNEL 1
C/A
B
A
BC/A
D/B
TSER
LSB MSB
LSB
CHANNEL 1
TCHCLK
TCHBLK
TSYSCLK
TSSYNC
CHANNEL 31
CHANNEL 32
1
Notes:
1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored
2. TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored).
3. TCHBLK is forced to one in the same channels as TSER is ignored (see Note 1)
4. The F-bit position (MSB position of channel 1) for the T1 frame is sampled and passed through the
transmit side elastic store (normally the transmit side formatter overwrites the F-bit position unless the
formatter is programmed to pass-through the F-bit position)
TSIG
D/B
CHANNEL 1
CHANNEL 31
CHANNEL 32
C/D
B
A
C/A
B
A
2,3
F4
相关PDF资料
PDF描述
DS21FT42N IC FRAMER T1 4X3 12CH IND 300BGA
VE-24R-IX-S CONVERTER MOD DC/DC 7.5V 75W
CONREVMCX003.062-L CONN RPMCX FEM EDGE MT 0.062"EXT
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