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参数资料
型号： DS21FF42N+
厂商： Maxim Integrated Products
文件页数： 30/114页
文件大小： 0K
描述： IC FRAMER T1 4X4 16CH 300-BGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 40
控制器类型： T1 调帧器
接口： 并行/串行
电源电压： 2.97 V ~ 3.63 V
电流 - 电源： 300mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 300-BBGA
供应商设备封装： 300-PBGA（27x27）
包装： 管件
DS21FT42/DS21FF42
22 of 114
Signal Name:
RMSYNC
Signal Description:
Receive Multiframe Sync
Signal Type:
Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK. This function is available when FMS = 1 (DS21Q41 emulation). This signal is not bonded
out in the DS21FF42/DS21FT42.
Signal Name:
RSYSCLK
Signal Description:
Receive System Clock
Signal Type:
Input
1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied
low in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz. This pin is
tied to the TSYSCLK signal in the DS21FF42/DS21FT42.
Signal Name:
RSIG
Signal Description:
Receive Signaling Output
Signal Type:
Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is
enabled. This function is available when FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:
RLOS/LOTC
Signal Description:
Receive Loss of Sync / Loss of Transmit Clock
Signal Type:
Output
A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to
either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q41
emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:
CLKSI
Signal Description:
8 MHz Clock Reference
Signal Type:
Input
A 1.544 MHz reference clock used in the generation of 8MCLK. This function is available when FMS =
0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:
8MCLK
Signal Description:
8 MHz Clock
Signal Type:
Output
A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is
available when FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
相关PDF资料
PDF描述
DS21FT42N IC FRAMER T1 4X3 12CH IND 300BGA
VE-24R-IX-S CONVERTER MOD DC/DC 7.5V 75W
CONREVMCX003.062-L CONN RPMCX FEM EDGE MT 0.062"EXT
PIC18F23K20-E/SP IC PIC MCU FLASH 4KX16 28-DIP
CONREVSMA006.031 CONN RPSMA FML EDGE MULTI 0.031"
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