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参数资料
| 型号： | DS21Q50LN |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 44/87页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER E1 QD IND 100LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 90 |
| 功能： | 收发器 |
| 接口： | E1 |
| 电路数： | 4 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | 230mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
| 包括： | AIS 警报检测器和发生器，回送功能，PRBS 发生器 / 检测器，远程检测器和发生器 |
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DS21Q50
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12.
PER-CHANNEL LOOPBACK
The DS21Q50 has per-channel loopback capability that can operate in one of two modes: remote per-
channel loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine
which channels are looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which
channels (if any) in the transmit direction should be replaced with the data from the receiver or, rather, off
the E1 line. In local per-channel loopback mode, PCLB1/2/3/4 determines which channels (if any) in the
receive direction should be replaced with the data from the transmit direction. If either mode is enabled,
then transmit and receive clocks and frame syncs must be synchronized. There are no restrictions on
which channels can be looped back or on how many channels can be looped back.
Register Name:
PCLB1, PCLB2, PCLB3, PCLB4
Register Description:
Per-Channel Loopback Registers
Register Address:
2B Hex, 2C Hex, 2D Hex, 2E Hex
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
Name
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
Name
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
Name
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
NAME
BIT
FUNCTION
CH1 to CH32
PCLB1.0 to 4.7
Per-Channel Loopback Control Bits
0 = do not loopback this channel
1 = loopback this channel
13.
ELASTIC STORE OPERATION
The DS21Q50 contains a two-frame (512 bits) elastic store for the receive direction. The elastic store is
used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous
(i.e., not frequency locked) backplane clock that can be 2.048MHz for normal operation or 4.096MHz,
8.192MHz, or 16.384MHz when using the IBO. The elastic store contains full-controlled slip capability.
If the receive elastic store is enabled (RCR.4 = 1), the user must provide a 2.048MHz clock to the
SYSCLK pin. If the IBO function is enabled, a 4.096MHz, 8.192MHz, or 16.384MHz clock must be
provided at the SYSCLK pin. The user can either provide a frame/multiframe sync at the RSYNC pin
(RCR.5 = 1) or have the RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5 = 0). If the
user wishes to obtain pulses at the frame boundary, RCR1.6 must be set to 0. If the user wishes to have
pulses occur at the multiframe boundary, RCR1.6 must be set to 1. If the elastic store is enabled, either
CAS (RCR.7 = 0) or CRC4 (RCR.7 = 1) multiframe boundaries are indicated through the RSYNC output.
See Section 19.1 for timing details. If the 512-bit elastic buffer either fills or empties, a controlled slip
occurs. If the buffer empties, a full frame of data (256 bits) is repeated at RSER, and the SR1.4 and RIR.3
bits are set to 1. If the buffer fills, a full frame of data is deleted, and the SR1.4 and RIR.4 bits are set to 1.
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| DS21Q50LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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| DS21Q55 | 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS21Q552 | 功能描述:网络控制器与处理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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