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参数资料
| 型号： | DS21Q50LN |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 56/87页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER E1 QD IND 100LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 90 |
| 功能： | 收发器 |
| 接口： | E1 |
| 电路数： | 4 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | 230mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
| 包括： | AIS 警报检测器和发生器，回送功能，PRBS 发生器 / 检测器，远程检测器和发生器 |
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DS21Q50
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1. INTRODUCTION
The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included
for this type of application: the interleave bus option (IBO) and a system clock synthesizer feature. The
IBO allows up to eight E1 data streams to be multiplexed onto a single high-speed PCM bus without
additional external logic. The system clock synthesizer feature allows any of the E1 lines to be selected as
the master source of clock for the system and for all the transmitters. This is also accomplished without
the need of external logic. Each of the four transceivers has a clock and data jitter attenuator that can be
assigned to either the transmit or receive path. In addition there is a single, undedicated clock jitter
attenuator that can be hardware configured as the user needs. Each transceiver also contains a PRBS
pattern generator and detector. Figure 18-1 shows a simplified typical application that terminates eight E1
lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The
16.384MHz system clock is derived and phased-locked to one of the eight E1 lines. On the receive side of
each port, an elastic store provides logical management of any slip conditions because of the
asynchronous relationship of the eight E1 lines. In this application, all eight transmitters are timed to the
selected E1 line.
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP
pins of the DS21Q50. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS21Q50 contains an active filter that reconstructs the analog received
signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of
0dB to -43dB, which allows the device to operate on cables over 2km in length. The receive framer
locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms
including, carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the receive elastic store
can be enabled in order to absorb the phase and frequency differences between the recovered E1 data
stream and an asynchronous backplane clock which is provided at the SYSCLK input. The clock applied
at the SYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The
transmit framer is independent from the receive in both the clock requirements and characteristics. The
transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
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相关代理商/技术参数 |
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| DS21Q50LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q50L-W+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q50N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| DS21Q55 | 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS21Q552 | 功能描述:网络控制器与处理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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