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| 型号： | DS21Q50LN |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 63/87页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER E1 QD IND 100LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 90 |
| 功能： | 收发器 |
| 接口： | E1 |
| 电路数： | 4 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | 230mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
| 包括： | AIS 警报检测器和发生器，回送功能，PRBS 发生器 / 检测器，远程检测器和发生器 |
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DS21Q50
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18.
INTERLEAVED PCM BUS OPERATION
In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses
to simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data
buses to be multiplexed into higher speed data buses, eliminating external hardware, saving board space
and cost. The DS21Q50 uses a channel interleave method. See Figure 19-4 and Figure 19-7 for details
about the channel interleave.
The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096MHz bus speed allows two
PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to
share a common bus. The 16.384MHz bus speed allows eight PCM data streams to share a common bus.
See Figure 18-1 for an example of four transceivers sharing a common 8.192MHz PCM bus. The receive
elastic stores of each transceiver must be enabled. Through the IBO register, the user can configure each
transceiver for a specific bus speed and position. For all IBO bus configurations, each transceiver is
assigned an exclusive position in the high-speed PCM bus. When the device is configured for IBO
operation, the TSYNCx pin should be configured as an output or as an input connected to ground. The
user cannot supply a TSYNCx signal in this mode.
Register Name:
IBOR
Register Description:
Interleave Bus Operation Register
Register Address:
1C Hex
Bit
7
6
5
4
3
2
1
0
Name
—
IBOTCS
SCS1
SCS0
IBOEN
DA2
DA1
DA0
NAME
BIT
FUNCTION
—
7
Not Assigned. Should be set to 0.
IBOTCS
6
IBO Transmit Clock Source
0 = TCLK pin is the source of transmit clock
1 = transmit clock is internally derived from the clock at the SYSCLK pin
SCS1
5
System Clock Select Bit 1 (Table 18-2)
SCS0
4
System Clock Select Bit 0 (Table 18-2)
IBOEN
3
Interleave Bus Operation Enable
0 = interleave bus operation disabled
1 = interleave bus operation enabled
DA2
2
Device Assignment Bit 3 (Table 18-1)
DA1
1
Device Assignment Bit 2 (Table 18-1)
DA0
0
Device Assignment Bit 1 (Table 18-1)
Table 18-1. IBO Device Assignment
DA2
DA1
DA0
FUNCTION
0
1st Device on bus
0
1
2nd Device on bus
0
1
0
3rd Device on bus
0
1
4th Device on bus
1
0
5th Device on bus
1
0
1
6th Device on bus
1
0
7th Device on bus
1
8th Device on bus
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