DS21Q50LN (Maxim) PDF资料下载 Datasheet(59/87 页)

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型号：	DS21Q50LN
厂商：	Maxim Integrated Products
文件页数：	59/87页
文件大小：	0K
描述：	IC TRANSCEIVER E1 QD IND 100LQFP
产品培训模块：	Lead (SnPb) Finish for COTS
产品变化通告：	Product Discontinuation 20/Feb/2012
标准包装：	90
功能：	收发器
接口：	E1
电路数：	4
电源电压：	3.14 V ~ 3.47 V
电流 - 电源：	230mA
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	100-LQFP
供应商设备封装：	100-LQFP（14x14）
包装：	托盘
包括：	AIS 警报检测器和发生器，回送功能，PRBS 发生器 / 检测器，远程检测器和发生器

DS21Q50

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16.5 Jitter Attenuators

The DS21Q50 contains an on-board clock and data jitter attenuator for each transceiver and a single,

undedicated “clock only” jitter attenuator. Figure 1-1 shows this undedicated jitter attenuator as the

alternate jitter attenuator.

Clock and Data Jitter Attenuators

The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to

buffer depths of either 32 or 128 bits through the LICR. The 128-bit mode is used in applications where

large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The

characteristics of the attenuators are shown in Figure 16-6. The jitter attenuators can be placed in either

the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also,

the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. For the jitter

attenuator to operate properly, a 2.048MHz clock (±50ppm) must be applied at the MCLK pin. On-board

circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the

TCLK pin to create a smooth jitter free clock that is used to clock data out of the jitter attenuator FIFO. It

is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the

transmit side. If the incoming jitter exceeds either 120 UIP-P (buffer depth is 128 bits) or 28 UIP-P (buffer

depth is 32 bits), the DS21Q50 divides the internal nominal 32.768MHz clock by either 15 or 17 instead

of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also

sets the JALT bit in the receive information register (RIR.5).

Undedicated Clock Jitter Attenuator

The undedicated jitter attenuator prepares a user-supplied clock for use as a transmission clock (TCLK).

AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL or

other synthesizers may contain too much jitter to be appropriate for transmission. Network requirements

limit the amount of jitter that can be transmitted onto the network. This feature is enabled by setting

SC1CR.7 = 1 in transceiver 1.

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