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| 型号： | DS21Q50LN |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 52/87页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER E1 QD IND 100LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 90 |
| 功能： | 收发器 |
| 接口： | E1 |
| 电路数： | 4 |
| 电源电压： | 3.14 V ~ 3.47 V |
| 电流 - 电源： | 230mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
| 包括： | AIS 警报检测器和发生器，回送功能，PRBS 发生器 / 检测器，远程检测器和发生器 |
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DS21Q50
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16.
LINE INTERFACE UNIT
The line interface unit in the DS21Q50 contains three sections: the receiver, which handles clock and data
recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line
interface control register (LICR), described below, controls each of these three sections.
Register Name:
LICR
Register Description:
Line Interface Control Register
Register Address:
17 Hex
Bit
7
6
5
4
3
2
1
0
Name
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
NAME
BIT
FUNCTION
L2
7
Line Build-Out Select Bit 2. Sets the transmitter build-out.
L1
6
Line Build-Out Select Bit 1. Sets the transmitter build-out.
L0
5
Line Build-Out Select Bit 0. Sets the transmitter build-out.
EGL
4
Receive Equalizer Gain Limit
0 = -12dB
1 = -43dB
JAS
3
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
2
Jitter Attenuator Buffer Depth Select
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
1
Disable Jitter Attenuator
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
0
Transmit Power-Down
0 = powers down the transmitter and three-states the TTIP and TRING pins
1 = normal transmitter operation
16.1 Receive Clock and Data Recovery
The DS21Q50 contains a digital clock-recovery system. See Figure 1-1 and Figure 16-2 for more details.
The device couples to the receive E1 shielded twisted pair or coax through a 1:1 transformer
(Table 16-4). The 2.048MHz clock attached at the MCLK pin is internally multiplied by 16 through an
internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the
PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This over-
sampling technique offers outstanding jitter tolerance (Figure 16-5).
Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and
RRING inputs. When no AMI signal is present at RTIP and RRING, a receive carrier loss (RCL)
condition occurs, and the RCLK is sourced from the clock applied at the MCLK pin. If the jitter
attenuator is either placed in the transmit path or is disabled, RCLK can exhibit slightly shorter high
cycles of the clock. This is because of the highly oversampled digital clock-recovery circuitry. If the jitter
attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores
the RCLK to being close to 50% duty cycle. See the Receive AC Characteristics in Section 21.4 for more
details.
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| DS21Q50LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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| DS21Q50N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| DS21Q55 | 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS21Q552 | 功能描述:网络控制器与处理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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