参数资料
型号: DS26334GNA3+
厂商: Maxim Integrated Products
文件页数: 109/121页
文件大小: 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
类型: 线路接口装置(LIU)
驱动器/接收器数: 16/16
规程: IEEE 1149.1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 256-LBGA,CSBGA
供应商设备封装: 256-CSBGA(17x17)
包装: 托盘
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
88 of 121
Register Name:
TEICR
Register Description:
Transmit Error Insertion Control Register
Register Address (LIUs 1–8):
08h
Register Address (LIUs 9–16):
28h
Bit #
7
6
5
4
3
2
1
0
Name
TEIR2
TEIR1
TEIR0
BEI
TSEI
MEIMS
Default
0
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]). These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value
of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A
TEIR[2:0] value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to
with a TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process,
the new error rate will be started after the next error is inserted.
Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be
inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause a bit error to be inserted.
Register Name:
BSR
Register Description:
BERT Status Register
Register Address (LIUs 1–8):
0Ch
Register Address (LIUs 9–16):
2Ch
Bit #
7
6
5
4
3
2
1
0
Name
PMS
BEC
Default
OOS
0
Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is
asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM=1) goes low.
Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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