参数资料
型号: DS26334GNA3+
厂商: Maxim Integrated Products
文件页数: 36/121页
文件大小: 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
类型: 线路接口装置(LIU)
驱动器/接收器数: 16/16
规程: IEEE 1149.1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 256-LBGA,CSBGA
供应商设备封装: 256-CSBGA(17x17)
包装: 托盘
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
21 of 121
Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters
TRANSMITTER FUNCTION
TELECOMMUNICATIONS COMPLIANCE
AMI Coding, B8ZS Substitution, DS1 Electrical Interface
ANSI T1.102
T1 Telecom Pulse Mask compliance
ANSI T1.403
T1 Telecom Pulse Mask compliance
ANSI T1.102
Transmit Electrical Characteristics for E1 Transmission
and Return Loss Compliance
ITU-T G.703
Table 5-3. Registers Related to Control of DS26334 Transmitters
REGISTER
NAME
FUNCTION
Transmit All Ones Enable
Transmit all ones enable.
Driver Fault Monitor Status
Driver fault status.
Driver Fault Monitor Interrupt Enable
Driver fault status interrupt mask.
Driver Fault Monitor Interrupt Status
Driver fault status interrupt mask.
Automatic Transmit All Ones Select
Transmit all ones enabled automatically on LOS.
Global Configuration
Global control of jitter attenuator, line coding and short
circuit protection.
Template Select Transmitter
The transmitter that the Template Select Transmitter
Register applies to.
Template Select
The TS2 to TS0 bits for selection of the templates for
transmitter and TIMPOFF and TIMPRIM bits to control
transmit impedance match.
Output Enable Configuration
These register bits can be used to enable the transmitter
outputs.
Master Clock Selection
Selects the MCLK frequency used for transmit and
receive.
Single-Rail Mode Select
This register can be used to select between single-rail
and dual-rail mode.
Line Code Selection
The individual transceiver line codes can be selected to
overwrite the global setting.
Transmit Power-Down Enable
Individual transmitters can be powered down.
Individual Jitter Attenuator Enable
Enables the jitter attenuator.
Individual Jitter Attenuator Position
Select
Selects whether jitter attenuator is in transmit or receive
path
Individual Jitter Attenuator FIFO
Depth Select
Selects depth of jitter attenuator FIFO.
Individual Jitter Attenuator FIFO
Limit Trip
Indicates jitter attenuator FIFO within 4 bits of its useful
limit.
Individual Short-Circuit Protection
Disable
This register allows the individual transmitters to have
short-circuit protection disable.
Short-Haul/Long-Haul Select
This selects between short-haul and long-haul templates.
Bit Error Rate Tester Control
This register allows mapping of the internal BERTs into
an individual transmit path.
Transmit Clock Invert
Inverts TCLK input.
BPV Error Insertion
Inserts a bipolar error in the transmit path when in single-
rail mode.
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