参数资料
型号: DS26334GNA3+
厂商: Maxim Integrated Products
文件页数: 50/121页
文件大小: 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
类型: 线路接口装置(LIU)
驱动器/接收器数: 16/16
规程: IEEE 1149.1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 256-LBGA,CSBGA
供应商设备封装: 256-CSBGA(17x17)
包装: 托盘
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
34 of 121
5.9
BERT
There are two bit error-rate testers available on the DS26334. One BERT can be mapped into LIUs 1–8 and the
other into LIUs 9–16 via the BTCR
Each BERT transmitter, by default, replaces data from TPOS and TNEG; each BERT receiver, by default, samples
recovered data from RTIP and RRING.
registers. The two BERTs operate independently of each other.
The BERT can be enabled to replace data received on RTIP and RRING via the BERTDIR bit in the BERT and
G.772 Monitoring Control Register (BGMC). In this mode, the SRMS bit determines whether data comes out single-
rail or dual-rail. BERT data can be sourced using the recovered clock, MCLK, or TCLK. In this mode of operation,
the BERT receiver samples data on TPOS and TNEG on the falling edge of TCLK. This function is useful for
testing the digital side of the LIU. If TCLK is selected as a source for this mode, the input TCLK will control the
BERT transmitter and receiver. If the recovered clock or MCLK is selected, the RCLK output needs to drive the
TCLK input in order for the BERT receiver to sync to the data.
5.9.1
General Description
The BERT is a software-programmable test pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudorandom
patterns with a generation polynomial of the form x
n + xy + 1, where n and y can take on values from 1 to 32 and
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern.
5.9.1.1
BERT Features
Programmable PRBS Pattern. The pseudorandom bit sequence (PRBS) polynomial (x
n + xy + 1) and
seed are programmable (length n = 1 to 32, tap y = 1 to n – 1, and seed = 0 to 2
n – 1).
Programmable Repetitive Pattern. The repetitive pattern length and pattern are programmable (the
length n = 1 to 32 and pattern = 0 to 2
n – 1).
24-Bit Error Count and 32-Bit Bit Count Registers
Programmable Bit-Error Insertion. Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10
n is programmable (n = 1 to 7).
Pattern Synchronization at a 10
-3 BER. Pattern synchronization is achieved even in the presence of a
random bit error rate (BER) of 10
-3.
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