参数资料
| 型号： | DS3106DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3106 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 计时，线路卡 |
| 已用 IC / 零件： | DS3106 |
| 已供物品： | 板，CD |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
_________________________________________________________________________________________DS3106DK
DFS are configured for programmable DFS operation, the DIG1 and DIG2 fields change to display the
programmable DFS frequency with a “P” prefix.
FSYNC is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be
inverted. MFSYNC is a 2kHz output that can be similarly configured.
Table 4-5. Mapping Between Output Clock Software Fields and DS3106 Register Fields
SOFTWARE FIELD
DIG1
DIG2
OC3 and OC6
FSYNC
MFSYNC
DS3106 REGISTER FIELDS
MCR6:DIG1SS, MCR7:DIG1F
MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF
OCR2 and OCR3
OCR4:FSEN, FSCR1:8KPUL, FSCR1:8KINV
OCR4:MFSEN, FSCR1:2KPUL, FSCR1:2KINV
4.7
DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
The DPLL frequency limits specify the hard and soft limits of the T0 DPLL frequency range. When the selected
reference exceeds the soft limit, the SOFTLIM LED turns red but the selected reference is not disqualified. If the
FLLOL (frequency limit loss of lock) box is checked in the DPLL LOCK CRITERIA box, when the selected
reference exceeds the hard limit the DPLL will lose lock (transition to LOL state).
The remaining fields are advanced topics. See Table 4-6 and the DS3106 data sheet for more details.
Table 4-6. Mapping Between DPLL Software Fields and DS3106 Register Fields
SOFTWARE FIELD
MCPDEN
USEMCPD
D180
COARSELIM
FINELIM
FLEN
CLEN
FLLOL
NALOL
HARD LIMIT
SOFT LIMIT
DS3106 REGISTER FIELDS
PHLIM2:MCPDEN
PHLIM2:USEMCPD
TEST1:D180
PHLIM2:COARSELIM
PHLIM1:FINELIM
PHLIM1:FLEN
PHLIM2:CLEN
DLIMIT3:FLLOL
PHLIM1:NALOL
HARDLIM[9:0] in DLIMIT1 and DLIMIT2
DLIMIT3:SOFTLIM
4.8
REFCLK Calibration
Any known frequency error in the local oscillator can be calibrated out inside the DS3106 by setting the ppm value
in the REFCLK CAL box. Also, the significant edge of the REFCLK signal can be selected in XOEDGE field.
Table 4-7. Mapping Between REFCLK Software Fields and DS3106 Register Fields
Rev: 012208
SOFTWARE FIELD
REFCLK slider/text box
XOEDGE
DS3106 REGISTER FIELDS
MCLKFREQ[15:0] in MCLK1 and MCLK2
MCR3:XOEDGE
11 of 32
相关PDF资料 |
PDF描述 |
|---|---|
| DS3144DK | KIT DEMO FOR DS3144 |
| DS3150DK | KIT DEMO DS3150 DS3/E3/STS-2 LIU |
| DS3153DK | KIT DEMO FOR DS3153 |
| DS3154DK | KIT DEMO FOR DS3154 |
| DS3170DK | KIT DESIGN FOR DS3170 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3106E12S-3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-3S | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4P | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4S | 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver Bulk |
| DS3106F-10SL-4S(621) | 制造商:Amphenol Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。