参数资料
| 型号： | DS3106DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/32页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3106 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 计时，线路卡 |
| 已用 IC / 零件： | DS3106 |
| 已供物品： | 板，CD |
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_________________________________________________________________________________________DS3106DK
4.9
Programmable DFS
When the Programmable DFS button in the upper-right corner of the main window is pressed, the Programmable
DFS window appears ( Figure 4-2 ). In this window one or more of the output DFS engines in the DS3106 can be
configured to synthesize a custom frequency that is a multiple of 2kHz (f < 77.76MHz) or a multiple of 8kHz (f ≤
311.04MHz). The desired frequency can be entered in the Target Output Clock Frequency (MHz) box at the top
of the window, and the software will perform the necessary computations to fill in the other numerical fields in
window.
The programmable DFS configuration can be applied to one or more DFS engines as specified in the Use
Programmable DFS box. Frequencies below 77.76MHz are typically synthesized by the DIG1 or DIG2 DFS
engine and brought out on CMOS/TTL output clock pin(s) by selecting DIG1 or DIG2 in the appropriate output
clock configuration field in the main window of the software. Frequencies of 77.76MHz or above must be
synthesized using an APLL DFS and its associated APLL, and are typically brought out on differential output clock
pin(s).
If a group of custom clock rates that are related to one another by factors of 1, 2, 4, 6, 8, 10, 12, 16, 20, 48, or 64
are needed, often the highest frequency clock can be produced through one of the APLL DFS blocks and then
various lower rate clocks can be selected on one or more of the output pins. Refer to the OCR2 and OCR3
registers in the DS3106 data sheet for details.
If the software-computed values for DFS Frequency (MHz) , DIG1/DIG2 Freq & APLL Input Freq , or APLL
Multiplier are manually overridden, the user must manually ensure that the DFS Frequency (MHz) falls within its
allowed range and that the APLL VCO Frequency falls within its allowed range. Note that the APL VCO
Frequency does not need to be within its allowed range if none of the APLL DFS blocks are selected for use.
The Register Configuration section of the Programmable DFS window shows the values that are written to the
DFSC1–DFSC15 registers to get the configuration specified in the upper part of the window. DFSC1–DFSC15 are
located at device addresses 1E0h–1EEh, respectively.
Rev: 012208
12 of 32
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相关代理商/技术参数 |
参数描述 |
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| DS3106E12S-3S(621) | 制造商:Amphenol Corporation 功能描述: |
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| DS3106F-10SL-4P | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4S | 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver Bulk |
| DS3106F-10SL-4S(621) | 制造商:Amphenol Corporation 功能描述: |
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