参数资料
| 型号： | DS3106DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/32页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3106 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 计时，线路卡 |
| 已用 IC / 零件： | DS3106 |
| 已供物品： | 板，CD |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
_________________________________________________________________________________________DS3106DK
Table 4-1. Mapping Between Input Clock Software Fields and DS3106 Register Fields
SOFTWARE FIELD
Input Clock Status LEDs 3 and 4
FREQ 3 and 4
LK MODE 3 and 4
SEL REF
FREQ (ppm)
PHASE (deg)
LEAKY BUCKET SETTINGS
DIVN
8K Polarity
Freq Range Enable
DS3106 REGISTER FIELDS
ISR2 register
LED red when ACT = 1, LOCK = 0
LED green when ACT = 0, LOCK = 0
LED magenta when LOCK = 1
ICR3 and ICR4:FREQ[3:0]
ICR3 and ICR4:LOCK8K, and DIVN
PTAB1:SELREF
FREQ1, FREQ2, and FREQ3 registers concatenated
PHASE1 and PHASE2 register concatenated
LBxU, LBxL, BLxS, LBxD (x = 1 to 4)
DIVN1, DIVN2
TEST1:8KPOL
MCR1:FREN
4.3
T0 DPLL
The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE text box. The STATE and
SRFAIL buttons represent latched status bits in the device. When the button is red, the corresponding latched
status bit has been set in the DS3106. Pressing the button clears the latched status bit and changes the color of
the button back to green. The STATE button indicates that the state of the T0 DPLL has changed since the last
time the button was pressed. SRFAIL indicates that the selected reference has failed since the last time the button
was pressed. The state of the T0 DPLL can be forced using the combo box to the left of the STATE text box.
The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3106 T0 DPLL). The
acquisition and locked bandwidths are set by the ABW and LBW fields, respectively, and the damping factor is set
by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0
DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of
the main window), the SOFTLIM LED turns red.
When the Freerun Holdover box is checked, the T0 DPLL will holdover at 0ppm with respect to the REFCLK
oscillator rather than at the long-term frequency average of the last valid input clock. When the Freerun Holdover
box is not checked, holdover type can be set to instant or averaged. The PALARM status LED and the phase
detector 2 ( PD2 ) fields are advanced topics. See Table 4-2 and the DS3106 data sheet for more details.
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3106 Register Fields
Rev: 012208
SOFTWARE FIELD
STATE combo box
STATE status box
FREQ
ABW
LBW
DAMP
STATE latched status button
SRFAIL
PALARM
SOFTLIM
AUTOBW
LIMINT
Freerun Holdover
Holdover Type
HO Ready
PD2 Enable
PD2G
PD2G8K
DS3106 REGISTER FIELDS
MCR1:T0STATE
OPSTATE:T0STATE
Fixed by T0 DPLL architecture
T0ABW
T0LBW
T0CR2:DAMP
MSR2:STATE
MSR2:SRFAIL
TEST1:PALARM
OPSTATE:T0SOFT
MCR9:AUTOBW
MCR9:LIMINT
MCR3:FRUNHO
HOCR3:AVG
VALSR2:HORDY
T0CR3:PD2EN
T0CR3:PD2G
T0CR2:PD2G8K
9 of 32
相关PDF资料 |
PDF描述 |
|---|---|
| DS3144DK | KIT DEMO FOR DS3144 |
| DS3150DK | KIT DEMO DS3150 DS3/E3/STS-2 LIU |
| DS3153DK | KIT DEMO FOR DS3153 |
| DS3154DK | KIT DEMO FOR DS3154 |
| DS3170DK | KIT DESIGN FOR DS3170 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3106E12S-3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-3S | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4P | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4S | 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver Bulk |
| DS3106F-10SL-4S(621) | 制造商:Amphenol Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。