参数资料
| 型号： | DS3106DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3106 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 计时，线路卡 |
| 已用 IC / 零件： | DS3106 |
| 已供物品： | 板，CD |
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_________________________________________________________________________________________DS3106DK
4.
Overview of the Software Interface
Figure 4-1. Software Main Screen
4.1
Global Configuration
In the upper-left corner of the main window are several global status and configuration fields. The ID field displays
the device part number and revision. The PORT field shows the COM port to which the DK board is connected.
The DEMO MODE checkbox, which is checked by default, must be unchecked to enable the software to
communicate with the DK board. The ENABLE POLLING checkbox, also checked by default, controls software
polling of the device. The RESET checkbox controls MCR1:RESET in the device. Finally, the SDH and SONET
radio buttons (which control device register field MCR3:SONSDH) specify whether 1.544MHz (SON) or 2.048MHz
(SDH) is an available frequency option for input clocks IC3 and IC4.
4.2
Input Clock Monitor, Divider, and Selector
This box occupying the lower left section of the main window contains the configuration and status associated with
input clocks IC3 and IC4.
Just to the right of the input clock numbers 3 and 4 are software LEDs that indicate the state of each input as
reported by its input monitor. These LEDs are red in the absence of any other condition. When a clock of the
correct frequency is applied to an input, the associated LED turns green when activity is detected. If an input is
disqualified by one of the DPLLs because the DPLL could not lock to it, the LED turns magenta.
In the middle of the box, the FREQ and LK MODE fields configure the frequency and lock mode (direct-lock, DIVN,
LOCK8K, or alternate direct-lock) for each input clock. Near the lower right corner is a field to configure the DIVN
divider used for inputs configured for DIVN mode.
The SEL REF field shows the selected reference for the DPLL. (Reminder: The DS3106 only supports manual
switching between IC3 and IC4, controlled by the SRCSW pin.) The FREQ and PHASE fields show the real-time
frequency and phase reported by the DPLL.
The field labeled 8K Polarity specifies the significant edge that the DS3106 will lock to when the input clock is
8kHz. The Freq Range Enable checkbox controls whether the DS3106 checks the input clocks for frequency
accuracy (within 10,000ppm).
Rev: 012208
8 of 32
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相关代理商/技术参数 |
参数描述 |
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| DS3106E12S-3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-3S | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4P | 制造商:Amphenol Corporation 功能描述: |
| DS3106F-10SL-4S | 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver 制造商:Amphenol 功能描述:10SL-4 vO Solder 500VDC / 700VAC 13A 125 Silver Bulk |
| DS3106F-10SL-4S(621) | 制造商:Amphenol Corporation 功能描述: |
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