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参数资料
型号： DS3112+
厂商： Maxim Integrated Products
文件页数： 132/133页
文件大小： 0K
描述： IC MUX TEMPE T3/E3 256-BGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 40
控制器类型： 调帧器，多路复用器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 150mA
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-PBGA（27x27）
包装： 管件
产品目录页面： 1419 (CN2011-ZH PDF)
DS3112
98 of 133
10.2 FEAC Status Register Description
Register Name:
FSR
Register Description:
FEAC Status Register
Register Address:
92h
Bit #
7
6
5
4
3
2
1
0
Name
—
RFI
RFCD
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
RFFO
RFFE
RFF5
RFF4
RFF3
RFF2
RFF1
RFF0
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Receive FEAC Codeword Detected (RFCD). This latched read-only event-status bit will be set to a one
each time the FEAC controller has detected and validated a new FEAC codeword. This bit will be cleared when
read and will not be set again until another new codeword is detected. The setting of this bit can cause a hardware
interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read.
Bit 14: Receive FEAC FIFO Empty (RFFE). This read-only real time status bit will be set to a one when the
Receive FEAC FIFO is empty and hence the RFF0 to RFF5 bits contain no valid information.
Bit 1: Receive FEAC Idle (RFI). This latched read-only event status bit will be set to a one each time the FEAC
controller has detected 16 consecutive ones following a valid codeword. This bit will be cleared when read. The
setting of this bit can cause a hardware interrupt to occur if the IERFI bit in the FEAC Control Register (FCR) is
set to one and the FEAC bit in the Interrupt Mask for MSR (IMSR) is set to one.
Bits 8 to 13: Receive FEAC FIFO Data (RFF0 to RFF5). Data from the Receive FEAC FIFO can be read from
these bits. The FEAC codeword is of the form ...0xxxxxx011111111... where the rightmost bit is received first.
These six bits are the debounced and integrated middle six bits of the second byte of the FEAC codeword (i.e., the
six “x” bits). RFF0 is the LSB and is received first while RFF5 is the MSB and is received last.
Bit 15: Receive FEAC FIFO Overflow (RFFO). This latched read-only event-status bit will be set to a one when
the receive FEAC controller has attempted to write to an already full Receive FEAC FIFO and current incoming
FEAC codeword is lost. This bit will be cleared when read and will not be set again until another FIFO overflow
occurs (i.e., the Receive FEAC FIFO has been read and then fills beyond capacity).
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相关代理商/技术参数
参数描述
DS3112+ 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS3112+W 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS3112D1 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS3112D1+ 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS3112DK 功能描述:网络开发工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V
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