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参数资料
| 型号： | DS80C410-FNY+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/102页 |
| 文件大小： | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 75MHz |
| 连通性： | 1 线，CAN，EBI/EMI，以太网，SIO，UART/USART |
| 外围设备： | 电源故障复位，WDT |
| 输入/输出数： | 64 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | ROM |
| RAM 容量： | 64K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
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External Reset Pins
The DS80C410 has both reset input (RST) and reset output (RSTOL) pins. The RSTOL pin supplies an active-low
reset output when the microcontroller is reset through a high on the RST pin, a timeout of the watchdog timer, a
crystal oscillator fail, or an internally detected power-fail. The timing of the RSTOL pin is dependent on the source
of the reset.
RESET TYPE/SOURCE
RSTOL
DURATION
Power-On Reset
65,536 tCLK (as described in Power Cycle Timing Characteristics)
External Reset
< 1.25 machine cycles
Power-Fail
65,536 tCLK (as described in Power Cycle Timing Characteristics)
Watchdog Timer Reset
Two machine cycles
Oscillator-Fail Detect
65,536 tCLK (as described in Power Cycle Timing Characteristics)
Idle Mode
Setting the IDLE bit (PCON.0) invokes the idle mode. Idle leaves internal clocks, serial ports, and timers running.
Power consumption drops because memory is not being accessed and instructions are not being executed. Since
clocks are running, the idle power consumption is a function of crystal frequency. The CPU can exit idle mode with
any interrupt or a reset. Because PMM consumes less power than idle mode, and leaves the timers and CPU
operating, idle mode is no longer recommended for new designs, and is included for backward-software
compatibility only.
Stop Mode
Setting the STOP bit of the power-control register (PCON.1) invokes stop mode. Stop mode is the lowest power
state (besides power off) since it turns off all internal clocking. All microcontroller operation ceases at the end of the
instruction that sets the STOP bit. The CPU invokes stop mode only when the CAN controller has been disabled
(through the SWINT or CRST bits in the C0C SFR) and when the Ethernet controller has been placed in sleep
mode. The CPU can exit stop mode through an external interrupt, Ethernet power-mode interrupt, CAN interrupt, or
a reset condition. Internally generated interrupts (timer, serial port, watchdog) cannot cause an exit from stop mode
because internal clocks are not active in stop mode. See the DC Electrical Specifications section for ICC1 and ICC3
maximum stop mode currents.
Bandgap Select
The DS80C410 provides two enhancements to stop mode. As described below, the device provides a bandgap
reference to determine power-fail interrupt and reset thresholds. The bandgap reference is controlled by the
bandgap select bit, BGS (EXIF.0). Setting BGS to a 1 keeps the bandgap reference enabled during stop mode.
The default or reset condition of the bit is logic 0, which disables the bandgap during stop mode. This bit does not
enable/disable the internal reference during full power, PMM, or idle modes.
With the bandgap reference enabled, the power-fail reset and power-fail interrupt sources are valid means for
leaving stop mode. This allows software to detect and compensate for a power supply sag or brownout, even when
in stop mode. When BGS = 1, the internal bandgap and associated comparator circuitry consume a small amount
of additional current during stop mode. If a user does not require a power-fail reset or interrupt while in stop mode,
the bandgap can remain disabled. Only the most power-sensitive applications should disable the bandgap
reference in stop mode, as this results in an uncontrolled power-down condition.
Ring Oscillator
The second enhancement to stop mode reduces power consumption and allows the device to restart instantly
when exiting stop mode. The ring oscillator is an internal clock that can optionally provide the clock source to the
microcontroller when exiting stop mode in response to an interrupt.
During stop mode the crystal oscillator is halted to maximize power savings. Typically 1ms to 7ms are required for
an external crystal to begin oscillating again once the device receives the exit stimulus. The ring oscillator, by
contrast, is a free-running digital oscillator that has no startup delay. The ring oscillator feature is enabled by setting
the ring oscillator select bit, RGSL (EXIF.1). If enabled, the microcontroller uses the ring oscillator as the clock
source to exit stop mode, resuming operation in less than 100ns. After 65,536 oscillations of the external clock
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS80C410-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| DS80C411 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C411-FNY | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| DS80C411-FNY+ | 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| DS80CH11 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:System Energy Manager |
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