参数资料
型号: DSP56301PW100
厂商: Freescale Semiconductor
文件页数: 103/124页
文件大小: 0K
描述: IC DSP 24BIT FIXED-POINT 208LQFP
标准包装: 36
系列: DSP563xx
类型: 定点
接口: 主机接口,SSI,SCI
时钟速率: 100MHz
非易失内存: ROM(9 kB)
芯片上RAM: 24kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 208-LQFP
供应商设备封装: 208-LQFP
包装: 托盘
DSP56301 Technical Data, Rev. 10
1-4
Freescale Semiconductor
Signals/Connections
1.1 Power
1.2 Ground
Table 1-2.
Power Inputs
Power Name
Description
VCCP
PLL Power
Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided
with an extremely low impedance path to the VCC power rail.
VCCQ
Quiet Power
Isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
VCCA
Address Bus Power
Isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
VCCD
Data Bus Power
Isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
VCCN
Bus Control Power
Isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors.
VCCH
Host Power
Isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
VCCS
ESSI, SCI, and Timer Power
Isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other internally. On
those packages, all power input except VCCP are labeled VCC.
Table 1-3.
Grounds
Ground Name
Description
GNDP
PLL Ground
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.
VCCP should be bypassed to GNDP by a 0.47 μF capacitor located as close as possible to the chip package.
GNDP1
PLL Ground 1
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.
GNDQ
Quiet Ground
Isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GNDA
Address Bus Ground
Isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external decoupling capacitors.
GNDD
Data Bus Ground
Isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
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