参数资料
型号: DSP56301PW100
厂商: Freescale Semiconductor
文件页数: 64/124页
文件大小: 0K
描述: IC DSP 24BIT FIXED-POINT 208LQFP
标准包装: 36
系列: DSP563xx
类型: 定点
接口: 主机接口,SSI,SCI
时钟速率: 100MHz
非易失内存: ROM(9 kB)
芯片上RAM: 24kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 208-LQFP
供应商设备封装: 208-LQFP
包装: 托盘
DSP56301 Technical Data, Rev. 10
2-18
Freescale Semiconductor
Specifications
Table 2-10.
DRAM Page Mode Timings, Three Wait States1, 2, 3
No.
Characteristics
Symbol
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
131
Page mode cycle time for two consecutive accesses of the
same direction
Page mode cycle time for mixed (read and write) accesses
tPC
4
× TC
3.5
× TC
50.0
43.7
40.0
35.0
ns
132
CAS assertion to data valid (read)
tCAC
2
× TC 5.7
19.3
14.3
ns
133
Column address valid to data valid (read)
tAA
3
× TC 5.7
31.8
24.3
ns
134
CAS deassertion to data not valid (read hold time)
tOFF
0.0
0.0
ns
135
Last CAS assertion to RAS deassertion
tRSH
2.5
× TC 4.0
27.3
21.0
ns
136
Previous CAS deassertion to RAS deassertion
tRHCP
4.5
× TC 4.0
52.3
41.0
ns
137
CAS assertion pulse width
tCAS
2
× TC 4.0
21.0
16.0
ns
138
Last CAS deassertion to RAS assertion5
BRW[1–0] = 00
BRW[1–0] = 01
BRW[1–0] = 10
BRW[1–0] = 11
tCRP
Not supported
3.75
× TC 6.0
4.75
× TC 6.0
6.75
× TC 6.0
40.9
53.4
78.4
31.5
41.5
61.5
ns
139
CAS deassertion pulse width
tCP
1.5
× TC 4.0
14.8
11.0
ns
140
Column address valid to CAS assertion
tASC
TC 4.0
8.5
6.0
ns
141
CAS assertion to column address not valid
tCAH
2.5
× TC 4.0
27.3
21.0
ns
142
Last column address valid to RAS deassertion
tRAL
4
× TC 4.0
46.0
36.0
ns
143
WR deassertion to CAS assertion
tRCS
1.25
× TC 4.0
11.6
8.5
ns
144
CAS deassertion to WR assertion
tRCH
0.75
× TC 4.0
5.4
3.5
ns
145
CAS assertion to WR deassertion
tWCH
2.25
× TC 4.2
23.9
18.3
ns
146
WR assertion pulse width
tWP
3.5
× TC 4.5
39.3
30.5
ns
147
Last WR assertion to RAS deassertion
tRWL
3.75
× TC 4.3
42.6
33.2
ns
148
WR assertion to CAS deassertion
tCWL
3.25
× TC 4.3
36.3
28.2
ns
149
Data valid to CAS assertion (write)
tDS
0.5
× TC – 4.8
2.0
0.2
ns
150
CAS assertion to data not valid (write)
tDH
2.5
× TC 4.0
27.3
21.0
ns
151
WR assertion to CAS assertion
tWCS
1.25
× TC 4.3
11.3
8.2
ns
152
Last RD assertion to RAS deassertion
tROH
3.5
× TC 4.0
39.8
31.0
ns
153
RD assertion to data valid
tGA
2.5
× TC 5.7
25.6
19.3
ns
154
RD deassertion to data not valid6
tGZ
0.0
0.0
ns
155
WR assertion to data active
0.75
× TC – 1.5
7.9
6.0
ns
156
WR deassertion to data high impedance
0.25
× TC
—3.1
—2.5
ns
Notes:
1.
The number of wait states for Page mode access is specified in the DCR.
2.
The refresh period is specified in the DCR.
3.
The asynchronous delays specified in the expressions are valid for DSP56301
.
4.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 ×
TC for read-after-read or write-after-write sequences).
5.
BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-
access.
6.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
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