参数资料
型号: DSP56301PW100
厂商: Freescale Semiconductor
文件页数: 48/124页
文件大小: 0K
描述: IC DSP 24BIT FIXED-POINT 208LQFP
标准包装: 36
系列: DSP563xx
类型: 定点
接口: 主机接口,SSI,SCI
时钟速率: 100MHz
非易失内存: ROM(9 kB)
芯片上RAM: 24kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 208-LQFP
供应商设备封装: 208-LQFP
包装: 托盘
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
iii
DSP56301 Features
High-Performance DSP56300 Core
80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V
Object code compatible with the DSP56000 core with highly parallel instruction set
Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24
× 24-bit parallel Multiplier-
Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support
under software control
Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes
optimized for DSP applications (including immediate offsets), internal instruction cache
controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast
auto-return interrupts
Direct Memory Access (DMA) with six DMA channels supporting internal and external
accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-
block-transfer interrupts; and triggering from interrupt lines and all peripherals
Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock
and output clock with skew elimination
Hardware debugging support including On-Chip Emulation (OnCE
) module, Joint Test Action
Group (JTAG) Test Access Port (TAP)
Internal Peripherals
32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless
interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three
transmitters (allows six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which
peripherals are enabled
Internal Memories
3 K
× 24-bit bootstrap ROM
8 K
× 24-bit internal RAM total
Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM
Size
Instruction Cache
Size
X Data RAM Size
Y Data RAM Size
Instruction
Cache
Switch
Mode
4096
× 24 bits
0
2048
× 24 bits
2048
× 24 bits
disabled
3072
× 24 bits
1024
× 24-bit
2048
× 24 bits
2048
× 24 bits
enabled
disabled
2048
× 24 bits
0
3072
× 24 bits
3072
× 24 bits
disabled
enabled
1024
× 24 bits
1024
× 24-bit
3072
× 24 bits
3072
× 24 bits
enabled
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