参数资料
型号: DSP56F826BU80E
厂商: Freescale Semiconductor
文件页数: 41/56页
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
标准包装: 90
系列: 56F8xx
核心处理器: 56800
芯体尺寸: 16-位
速度: 80MHz
连通性: EBI/EMI,SCI,SPI,SSI
外围设备: POR,WDT
输入/输出数: 46
程序存储器容量: 67KB(33.5K x 16)
程序存储器类型: 闪存
RAM 容量: 4.5K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 2.75 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
56F826 Technical Data, Rev. 14
46
Freescale Semiconductor
Figure 3-28 TXD Pulse Width
3.13 JTAG Timing
Figure 3-29 Test Clock Input Timing Diagram
Table 3-17 JTAG Timing1, 3
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
fOP
DC
10
MHz
TCK cycle time
tCY
100
ns
TCK clock pulse width
tPW
50
ns
TMS, TDI data set-up time
tDS
0.4
ns
TMS, TDI data hold time
tDH
1.2
ns
TCK low to TDO data valid
tDV
26.6
ns
TCK low to TDO tri-state
tTS
23.5
ns
TRST assertion time
tTRST
50
ns
DE assertion time
tDE
4T
ns
TXD
SCI receive
data pin
(Input)
TXDPW
TCK
(Input)
VM
VIL
VM = VIL + (VIH – VIL)/2
VM
VIH
tPW
tCY
tPW
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