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参数资料
| 型号： | DSP56F827FG80E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 30/60页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR 16BIT 128-LQFP |
| 标准包装： | 72 |
| 系列： | 56F8xx |
| 核心处理器： | 56800 |
| 芯体尺寸： | 16-位 |
| 速度： | 80MHz |
| 连通性： | EBI/EMI，SCI，SPI，SSI |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 64 |
| 程序存储器容量： | 136KB（68K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 5K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 2.25 V ~ 2.75 V |
| 数据转换器： | A/D 10x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 128-LQFP |
| 包装： | 托盘 |
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56F827 Technical Data, Rev. 12
36
Freescale Semiconductor
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
tRA
275,000T
128T
—
ns
RESET Deassertion to First External Address Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
15T
—
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
tIRI
13T
—
ns
IRQA Width Assertion to Recover from Stop State4
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
tIW
2T
—
ns
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
275,000T
12T
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
275,000T
12T
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
275,000T
12T
ns
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相关代理商/技术参数 |
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|---|---|
| DSP56F827FG80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
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| DSP56F827PB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56F827 16-Bit Hybrid Controller Product Brief |
| DSP56F827PB/D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller |
| DSP56F8XXBLUM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56F8xx Serial Bootloader User Manual |
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