参数资料
型号: DSP56F827FG80E
厂商: Freescale Semiconductor
文件页数: 5/60页
文件大小: 0K
描述: IC HYBRID CTRLR 16BIT 128-LQFP
标准包装: 72
系列: 56F8xx
核心处理器: 56800
芯体尺寸: 16-位
速度: 80MHz
连通性: EBI/EMI,SCI,SPI,SSI
外围设备: POR,PWM,WDT
输入/输出数: 64
程序存储器容量: 136KB(68K x 16)
程序存储器类型: 闪存
RAM 容量: 5K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 2.75 V
数据转换器: A/D 10x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 128-LQFP
包装: 托盘
Signals and Package Information
56F827 Technical Data, Rev. 12
Freescale Semiconductor
13
D0
(GPIOG0)
125
Input/Output
Data Bus—D0–D15 specify the data for external Program or Data memory
accesses. D0-D15 are tri-stated when the external bus is inactive.
Port G GPIO—These 16 General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
D1
(GPIOG1)
126
D2
(GPIOG2)
127
D3
(GPIOG3)
128
D4
(GPIOG4)
1
D5
(GPIOG5)
2
D6
(GPIOG6)
3
D7
(GPIOG7)
6
D8
(GPIOG8)
7
D9
(GPIOG9)
8
D10
(GPIOG10)
9
D11
(GPIOG11)
10
D12
(GPIOG12)
11
D13
(GPIOG13)
12
D14
(GPIOG14)
13
D15
(GPIOG15)
14
PS
(PCS0)
18
Output
Program Memory Select—PS is asserted low for external program memory
access. This pin can also be programmed as a programmable chip select.
DS
(PCS1)
17
Output
Data Memory Select—DS is asserted low for external Data memory access.
This pin can also be programmed as a programmable chip select.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
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