- 您现在的位置：买卖IC网 > PDF目录16057 > EF-ISE-LOG-FL (Xilinx Inc)DESIGN SUITE LOGIC EDITION PDF资料下载
参数资料
| 型号： | EF-ISE-LOG-FL |
| 厂商： | Xilinx Inc |
| 文件页数： | 30/50页 |
| 文件大小： | 0K |
| 描述： | DESIGN SUITE LOGIC EDITION |
| 标准包装： | 1 |
| 系列： | ISE® 设计套件 |
| 类型： | 集成软件环境（ISE） |
| 适用于相关产品： | Xilinx FPGAs |
| 其它名称： | Q5689019A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页
Chapter 2: What’s New in PlanAhead Software
New Clock Planning View Layout
There is a new Clock Planning view layout to facilitate the planning and placement of
clock resources in the design. The Clock Planning view layout is available from the Layout
menu or from the pulldown Layout Selector in the toolbar menu.
Save Workspace View with Custom Layout Save
In customized GUI layouts, the PlanAhead software also saves changes to the Workspace
view layout, such as the Device view and Project Summary, along with other user-defined
layout changes.
Hierarchical Design Methodology Support
The PlanAhead software has added the ability to configure partition settings in both the
synthesis and implementation run settings dialogs. This allows the ability to control
partition behavior directly in the run settings section of the tool. Once a partition has been
selected in the RTL or Netlist views, there is a new option in the Flow Navigator to control
the partition settings for both synthesis and implementation.
Pin Planning Features
Initial 7 Series SSN Report
Support for Simultaneous Switching Noise (SSN) signal integrity checks and
recommendations have been added for certain 7 series devices. This report will likely be
enhanced based on further characterization in the future. Unsupported devices are
indicated when running the report, using either the Tools > Run Noise Analysis
command or the equivalent Tcl command.
7 Series HP/HR Bank Support
The PlanAhead software supports HP and HR Bank visualization for 7 series devices in the
Device and Package views.
Automatically Sort Package Pins View
After setting the Device Configuration Mode, the PlanAhead software offers the option to
automatically sort the Package Pins view by the Config column so newly configured pins
are listed first.
Export IBIS Model Command Removed
IBIS model generation is not supported in the PlanAhead software. PlanAhead 13.1
provided a Tcl command and a menu command to export an IBIS model configured for
your device, which issued a warning message stating that this capability was not
supported. This menu option and Tcl command have been removed until the feature is
fully supported. The standalone IBISWriter tool supports IBIS model generation for
Spartan?-6, Virtex?-6 and 7 series devices. Refer to the Command Line Tools Users Guide
(UG628) for more information on using the IBISWriter.
30
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
相关PDF资料 |
PDF描述 |
|---|---|
| VE-JVN-EZ-F4 | CONVERTER MOD DC/DC 18.5V 25W |
| VE-JVM-EZ-F2 | CONVERTER MOD DC/DC 10V 25W |
| VE-JVM-EY-S | CONVERTER MOD DC/DC 10V 50W |
| VE-JVL-EZ-F3 | CONVERTER MOD DC/DC 28V 25W |
| M3BFK-4018J | IDC CABLE - MSR40K/MC40G/MCF40K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EF-ISE-LOG-NL | 功能描述:DESIGN SUITE LOGIC EDITION ISE12 RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-FL | 功能描述:ISE DESIGN SYST FLOATING LICENSE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-NL | 功能描述:SOFTWARE ISE SYS EDITION RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EFJ02-001M | 制造商:Black Box Corporation 功能描述:TOSLINK TO MINI PLUG PATCH COR |
| EFJ04-001M | 制造商:Black Box Corporation 功能描述:PREMIUM GRADE DIGITAL OPTICAL CABLE 1 METER |
发布紧急采购，3分钟左右您将得到回复。