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| 型号： | EF-ISE-LOG-FL |
| 厂商： | Xilinx Inc |
| 文件页数： | 32/50页 |
| 文件大小： | 0K |
| 描述： | DESIGN SUITE LOGIC EDITION |
| 标准包装： | 1 |
| 系列： | ISE® 设计套件 |
| 类型： | 集成软件环境（ISE） |
| 适用于相关产品： | Xilinx FPGAs |
| 其它名称： | Q5689019A |
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Chapter 2: What’s New in PlanAhead Software
Design Preservation RTL Support
PlanAhead 13 enhances support for design preservation flows by adding incremental
compilation for RTL synthesis of partitions with XST. The design preservation flow allows
a designer to mark portions of a design to be preserved in subsequent iterations and
enabled incremental compilation. In prior releases, design preservation was only
supported post synthesis. RTL-level control was added to provide designers an easier to
use flow to control partitions throughout the design flow from synthesis through
implementation within the PlanAhead user interface.
See the Hierarchical Design Methodology Guide (UG748) and Chapter 13, Hierarchical Design
Techniques, in the PlanAhead User Guide (UG632) for more information.
Partial Reconfiguration Support
PlanAhead provides an interface to Partial Reconfiguration with appropriate licensing.
See the Partial Reconfiguration User Guide (UG702) for more information.
Project Navigator Project File (.xise) Support
The New Project wizard lets you specify an ISE project file without requiring the
specification of all project sources. The PlanAhead software:
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Parses the XISE project file
Adds RTL and simulation sources, including CORE Generator? software cores and
Block Memory Model (BMM) file
PlanAhead can now also determine relevant run options for Synthesis and
Implementation tools and can configure the default run to match based on settings in the
XISE project file.
New and Modified Project Management Features
The following subsections describe the new and modified features in PlanAhead projects.
In PlanAhead 13, you can:
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Import sources from Project Navigator
Order source files automatically or manually for proper compilation by XST
Discover the top-module name automatically
Support ‘include statements inside HDL more robustly
Support Xilinx Synthesis Technology (XST) XCF constraint files
Identify unused source files
Launch Runs without copying sources to the Run directory
Archive projects
Customize the Text Editor font
32
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
相关PDF资料 |
PDF描述 |
|---|---|
| VE-JVN-EZ-F4 | CONVERTER MOD DC/DC 18.5V 25W |
| VE-JVM-EZ-F2 | CONVERTER MOD DC/DC 10V 25W |
| VE-JVM-EY-S | CONVERTER MOD DC/DC 10V 50W |
| VE-JVL-EZ-F3 | CONVERTER MOD DC/DC 28V 25W |
| M3BFK-4018J | IDC CABLE - MSR40K/MC40G/MCF40K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EF-ISE-LOG-NL | 功能描述:DESIGN SUITE LOGIC EDITION ISE12 RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-FL | 功能描述:ISE DESIGN SYST FLOATING LICENSE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-NL | 功能描述:SOFTWARE ISE SYS EDITION RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EFJ02-001M | 制造商:Black Box Corporation 功能描述:TOSLINK TO MINI PLUG PATCH COR |
| EFJ04-001M | 制造商:Black Box Corporation 功能描述:PREMIUM GRADE DIGITAL OPTICAL CABLE 1 METER |
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