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参数资料
| 型号： | EF-ISE-LOG-FL |
| 厂商： | Xilinx Inc |
| 文件页数： | 31/50页 |
| 文件大小： | 0K |
| 描述： | DESIGN SUITE LOGIC EDITION |
| 标准包装： | 1 |
| 系列： | ISE® 设计套件 |
| 类型： | 集成软件环境（ISE） |
| 适用于相关产品： | Xilinx FPGAs |
| 其它名称： | Q5689019A |
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PlanAhead Software 13.1
Improved Tcl Online Help and Documentation
Additional details have been added to Tcl command reference documentation, available in
the PlanAhead Software Tcl Command Reference Guide (UG789)
ommands.pdf ), and the online help text available through the Tcl help command.
PlanAhead Software 13.1
This section provides an overview of the PlanAhead software 13.1 release. See the related
chapters in the PlanAhead User Guide (UG632), for more information.
ISE Simulator Integration
The PlanAhead software has integrated the Xilinx ISE Simulator (ISim) into the design
flow. This new integration enables development and verification of designs completely
within the PlanAhead user interface. PlanAhead now has support for simulation-only
sources added to the project, which is performed either in the new project wizard or in the
add sources dialog. The Flow Navigator provides access to ISE Simulator.
You can invoke ISim:
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After RTL Design for behavioral simulation
After Implementation for timing simulation
Hierarchical Design Methodology Support
The PlanAhead software supports the Hierarchical Design features as described in the
following subsections.
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Incremental XST flow in RTL projects
Importing a partition into a different hierarchy than the one in which the partition
was created
AREA_GROUPS within partitions
Black box support in Synthesis and Implementation
Boundary optimization for constants and unconnected inputs and outputs on
partition ports
Defining partitions for Design Preservation in Netlist-based projects
Team-Based Design Support
PlanAhead 13 adds support for new team-based design methodology. Team-based design
supports multiple engineers implementing at a module level within a design to work in
parallel. The flow then supports assembling the module-level runs by a team leader at the
top level with support for preservation levels to control the placement and routing
information that is kept during import.
See the Hierarchical Design Methodology Guide (UG748) and Chapter 13, Hierarchical Design
Techniques, in the PlanAhead User Guide (UG632) for more information.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
31
相关PDF资料 |
PDF描述 |
|---|---|
| VE-JVN-EZ-F4 | CONVERTER MOD DC/DC 18.5V 25W |
| VE-JVM-EZ-F2 | CONVERTER MOD DC/DC 10V 25W |
| VE-JVM-EY-S | CONVERTER MOD DC/DC 10V 50W |
| VE-JVL-EZ-F3 | CONVERTER MOD DC/DC 28V 25W |
| M3BFK-4018J | IDC CABLE - MSR40K/MC40G/MCF40K |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EF-ISE-LOG-NL | 功能描述:DESIGN SUITE LOGIC EDITION ISE12 RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-FL | 功能描述:ISE DESIGN SYST FLOATING LICENSE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-NL | 功能描述:SOFTWARE ISE SYS EDITION RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EFJ02-001M | 制造商:Black Box Corporation 功能描述:TOSLINK TO MINI PLUG PATCH COR |
| EFJ04-001M | 制造商:Black Box Corporation 功能描述:PREMIUM GRADE DIGITAL OPTICAL CABLE 1 METER |
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