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参数资料
| 型号： | EP20K100BC324-3 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA324 |
| 文件页数： | 66/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BC324-3 |
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Altera Corporation
7
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers the in-system programmability (ISP)-capable EPC2
configuration devices, which configure APEX 20K devices via a serial
data stream. Moreover, APEX 20K devices contain an optimized interface
that permits microprocessors to configure APEX 20K devices serially or in
parallel, and synchronously or asynchronously. The interface also enables
microprocessors to treat APEX 20K devices as memory and configure the
device by writing to a virtual memory location, making reconfiguration
easy.
1
Contact Altera for information on future configuration devices.
After an APEX 20K device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
APEX 20K devices are supported by Altera’s Quartus development
system, a single, integrated package that offers HDL and schematic design
entry, compilation and logic synthesis, full simulation and worst-case
timing analysis, SignalTap logic analysis, and device configuration. The
Quartus software runs on Windows-based PCs, Sun SPARCstations, and
HP 9000 Series 700/800 workstations.
The Quartus software provides NativeLink interfaces to other industry-
standard PC- and UNIX workstation-based EDA tools. For example,
designers can invoke the Quartus software from within third-party design
tools. Further, the Quartus software contains built-in optimized synthesis
libraries; synthesis tools can use these libraries to optimize designs for
APEX 20K devices. For example, the Synopsys Design Compiler library,
supplied with the Quartus development system, includes DesignWare
functions optimized for the APEX 20K architecture.
Functional
Description
APEX 20K devices incorporate LUT-based logic, product-term-based
logic, and memory into one device. Signal interconnections within
APEX 20K devices (as well as to and from device pins) are provided by the
FastTrack Interconnect—a series of fast, continuous row and column
channels that run the entire length and width of the device.
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100BI324-1 | LOADABLE PLD, PBGA324 |
| EP20K100BI324-2 | LOADABLE PLD, PBGA324 |
| EP20K100BI324-3 | LOADABLE PLD, PBGA324 |
| EP20K100BC484-1 | LOADABLE PLD, PBGA484 |
| EP20K100BC484-2 | LOADABLE PLD, PBGA484 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100BC356-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BC356-1V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K100BC356-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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