参数资料
型号: EPF10K200S
英文描述: Programmable Logic
中文描述: 可编程逻辑
文件页数: 71/138页
文件大小: 2116K
代理商: EPF10K200S
38
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Clamping diodes are controlled on a pin-by-pin basis via a logic option in
the MAX+PLUS II software. When VCCIO is 3.3 V, a pin that has the
clamping diode turned on can be driven by a 2.5-V or 3.3-V signal, but not
a 5.0-V signal. When VCCIO is 2.5 V, a pin that has the clamping diode
turned on can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal.
However, a clamping diode can be turned on for a subset of pins, which
allows devices to bridge between a 3.3-V PCI bus and a 5.0-V device.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of approximately
2.9 ns. The fast slew rate should be used for speed-critical outputs in
systems that are adequately protected against noise. Designers can specify
the slew rate on a pin-by-pin basis during design entry or assign a default
slew rate to all pins on a device-wide basis. The slow slew rate setting
affects only the falling edge of the output.
Open-Drain Output Option
FLEX 10K devices provide an optional open-drain (electrically equivalent
to an open-collector) output for each I/O pin. This open-drain output
enables the device to provide system-level control signals (e.g., interrupt
and write enable signals) that can be asserted by any of several devices. It
can also provide an additional wired-OR plane. Additionally, the
MAX+PLUS II software can convert tri-state buffers with grounded data
inputs to open-drain pins automatically.
Open-drain output pins on FLEX 10K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin
is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-
drain pin will only drive low or tri-state; it will never drive high. The rise
time is dependent on the value of the pull-up resistor and load
impedance. The IOL current specification should be considered when
selecting a pull-up resistor.
Output pins on 5.0-V FLEX 10K devices with VCCIO = 3.3 V or 5.0 V (with
a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input
pins. In this case, the pull-up transistor will turn off when the pin voltage
exceeds 3.3 V. Therefore, the pin does not have to be open-drain.
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EPF10K200SBC356-1X 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 1248 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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