参数资料
| 型号： | EPF6024ATC144-3N |
| 厂商： | Altera |
| 文件页数： | 11/52页 |
| 文件大小： | 0K |
| 描述： | IC FLEX 6000 FPGA 24K 144-TQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 180 |
| 系列： | FLEX 6000 |
| LAB/CLB数： | 196 |
| 逻辑元件/单元数： | 1960 |
| 输入/输出数： | 117 |
| 门数： | 24000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
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Altera Corporation
19
FLEX 6000 Programmable Logic Device Family Data Sheet
A row channel can be driven by an LE or by one of two column channels.
These three signals feed a 3-to-1 multiplexer that connects to six specific
row channels. Row channels drive into the local interconnect via
multiplexers.
Each column of LABs is served by a dedicated column interconnect. The
LEs in an LAB can drive the column interconnect. The LEs in an LAB, a
column IOE, or a row interconnect can drive the column interconnect. The
column interconnect can then drive another row’s interconnect to route
the signals to other LABs in the device. A signal from the column
interconnect must be routed to the row interconnect before it can enter an
LAB.
Each LE has a FastTrack Interconnect output and a local output. The
FastTrack interconnect output can drive six row and two column lines
directly; the local output drives the local interconnect. Each local
interconnect channel driven by an LE can drive four row and two column
channels. This feature provides additional flexibility, because each LE can
drive any of ten row lines and four column lines.
In addition, LEs can drive global control signals. This feature is useful for
distributing internally generated clock, asynchronous clear, and
asynchronous preset signals. A pin-driven global signal can also drive
data signals, which is useful for high-fan-out data signals.
Each LAB drives two groups of local interconnects, which allows an LE to
drive two LABs, or 20 LEs, via the local interconnect. The row-to-local
multiplexers are used more efficiently, because the multiplexers can now
drive two LABs. Figure 10 shows how an LAB connects to row and
column interconnects.
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