参数资料
型号: EPF6024ATC144-3N
厂商: Altera
文件页数: 46/52页
文件大小: 0K
描述: IC FLEX 6000 FPGA 24K 144-TQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 180
系列: FLEX 6000
LAB/CLB数: 196
逻辑元件/单元数: 1960
输入/输出数: 117
门数: 24000
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
50
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Operating Modes
The FLEX 6000 architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers
up. This process of physically loading the SRAM data into a FLEX
6000 device is known as configuration. During initialization—a
process that occurs immediately after configuration—the device
resets registers, enables I/O pins, and begins to operate as a logic
device. The I/O pins are tri-stated during power-up, and before and
during configuration. The configuration and initialization processes
of a device are referred to as command mode; normal device operation
is called user mode.
SRAM configuration elements allow FLEX 6000 devices to be
reconfigured in-circuit by loading new configuration data into the
device. Real-time reconfiguration is performed by forcing the device
into command mode with a device pin, loading different
configuration data, reinitializing the device, and resuming user-
mode operation. The entire reconfiguration process requires less
than 100 ms and is used to dynamically reconfigure an entire system.
Also, in-field system upgrades can be performed by distributing new
configuration files.
Configuration Schemes
The configuration data for a FLEX 6000 device can be loaded with
one of three configuration schemes, which is chosen on the basis of
the target application. An EPC1 or EPC1441 configuration device or
intelligent controller can be used to control the configuration of a
FLEX 6000 device, allowing automatic configuration on system
power-up.
Multiple FLEX 6000 devices can be configured in any of the three
configuration schemes by connecting the configuration enable input
(nCE) and configuration enable output (nCEO) pins on each device.
Table 40 shows the data sources for each configuration scheme.
Table 40. Configuration Schemes
Configuration Scheme
Data Source
Configuration device
EPC1 or EPC1441 configuration device
Passive serial (PS)
BitBlaster
TM, ByteBlasterMVTM, or MasterBlasterTM
download cables, or serial data source
Passive serial asynchronous
(PSA)
BitBlaster, ByteBlasterMV, or MasterBlaster
download cables, or serial data source
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