参数资料
| 型号： | EPF6024ATC144-3N |
| 厂商： | Altera |
| 文件页数： | 45/52页 |
| 文件大小： | 0K |
| 描述： | IC FLEX 6000 FPGA 24K 144-TQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 180 |
| 系列： | FLEX 6000 |
| LAB/CLB数： | 196 |
| 逻辑元件/单元数： | 1960 |
| 输入/输出数： | 117 |
| 门数： | 24000 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页当前第45页第46页第47页第48页第49页第50页第51页第52页
Altera Corporation
5
FLEX 6000 Programmable Logic Device Family Data Sheet
Functional
Description
The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs).
Each LE includes a 4-input look-up table (LUT), which can implement any
4-input function, a register, and dedicated paths for carry and cascade
chain functions. Because each LE contains a register, a design can be easily
pipelined without consuming more LEs. The specified gate count for
FLEX 6000 devices includes all LUTs and registers.
LEs are combined into groups called logic array blocks (LABs); each LAB
contains 10 LEs. The Altera software automatically places related LEs into
the same LAB, minimizing the number of required interconnects. Each
LAB can implement a medium-sized block of logic, such as a counter or
multiplexer.
Signal interconnections within FLEX 6000 devices—and to and from
device pins—are provided via the routing structure of the FastTrack
Interconnect. The routing structure is a series of fast, continuous row and
column channels that run the entire length and width of the device. Any
LE or pin can feed or be fed by any other LE or pin via the FastTrack
Interconnect. See “FastTrack Interconnect” on page 17 of this data sheet
for more information.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can
be driven by the local interconnect of that LAB. This feature allows fast
clock-to-output times of less than 8 ns when a pin is driven by any of the
10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and
column interconnect. I/O pins can drive the LE registers via the row and
column interconnect, providing setup times as low as 2 ns and hold times
of 0 ns. IOEs provide a variety of features, such as JTAG BST support,
slew-rate control, and tri-state buffers.
Figure 1 shows a block diagram of the FLEX 6000 OptiFLEX architecture.
Each group of ten LEs is combined into an LAB, and the LABs are
arranged into rows and columns. The LABs are interconnected by the
FastTrack Interconnect. IOEs are located at the end of each FastTrack
Interconnect row and column.
相关PDF资料 |
PDF描述 |
|---|---|
| AT28C256F-15SU | IC EEPROM 256KBIT 150NS 28SOIC |
| EPF6024ATC144-3 | IC FLEX 6000 FPGA 24K 144-TQFP |
| AT28HC256E-12TU | IC EEPROM 256KBIT 120NS 28TSOP |
| AGL400V5-CS196 | IC FPGA 1KB FLASH 400K 196-CSP |
| AT27C4096-55JU | IC OTP 4MBIT 55NS 44PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF8001GM | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:10/100 LAN Interface Module with Common Mode Termination |
| EPF8007M | 制造商:PCA 功能描述: |
| EPF8008 | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:High Speed LAN Interface Module |
| EPF8008A | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:High Speed LAN Interface Module |
| EPF8010GH | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:10/100Base-TX Interface Module with Enhanced Common Mode Attenuation |
发布紧急采购，3分钟左右您将得到回复。