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参数资料
| 型号： | EVAL-AD9880-ABZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/64页 |
| 文件大小： | 0K |
| 描述： | KIT MODULE VIDEO INPUT AD9880 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要属性： | HDMI 接收器和模拟接口 |
| 次要属性： | 3 路 8 位 150MSPS ADC |
| 已供物品： | 板 |
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AD9880
Rev. 0 | Page 20 of 64
HDMI RECEIVER
The HDMI receiver section of the AD9880 allows the reception
of a digital video stream, which is backward-compatible with
DVI and able to accommodate not only video of various for-
mats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of
audio. Infoframes are transmitted carrying information about
the video format, audio clocks, and many other items necessary
for a monitor to utilize fully the information stream available.
The earlier digital visual interface (DVI) format was restricted
to an RGB 24 bit color space only. Embedded in this data
stream were Hsyncs, Vsyncs and display enable (DE) signals,
but no audio information. The HDMI specification allows
trans-mission of all the DVI capabilities, but adds several
YCrCb formats that make the inclusion of a programmable
color space converter (CSC) a very desirable feature. With this,
the scaler following the AD9880 can specify that it always
wishes to receive a particular format, for instance, 4:2:2 YCrCb
regardless of the transmitted mode. If RGB is sent, the CSC can
easily convert that to 4:2:2 YCrCb while relieving the scaler of
this task.
In addition, the HDMI specification supports the transmission
of up to eight channels of S/PDIF or I2S audio. The audio
information is packetized and transmitted during the video
blanking periods along with specific information about the
clock frequency. Part of this audio information (Audio
Infoframe) tells the user how many channels of audio, where
they should be placed, information regarding the source (make,
model), and other data.
DE GENERATOR
The AD9880 has an onboard generator for DE, for start of
active video (SAV), and for end of active video (EAV), all of
which are necessary for describing the complete data stream for
a BT656 compatible output. In addition to this particular
output, it is possible to generate the DE for cases in which a
scaler is not planned to be used. This signal alerts the following
circuitry as to which are displayable video pixels.
4:4:4 TO 4:2:2 FILTER
The AD9880 contains a filter which allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.
Input Color space to Output Color space
The AD9880 can accept a wide variety of input formats and
either retain that format or convert to another. Input formats
supported are
4:4:4 YCrCb 8 bit
4:2:2 YCrCb 8, 10, and 12 bit
RGB 8-bit
Output modes supported are
4:4:4 YCrCb 8 bits
4:2:2 YCrCb 8, 10, and 12 bits
Dual 4:2:2 YCrCb 8 bits.
Color space Conversion (CSC) Matrix
The color space conversion (CSC) matrix in the AD9880
consists of three identical processing channels. In each channel,
three input values are multiplied by three separate coefficients.
Also included are an offset value for each row of the matrix and
a scaling multiple for all values. Each value has a 13 bit twos
complement resolution to ensure the signal integrity is main-
tained. The CSC is designed to run at speeds up to 150 MHz
supporting resolutions up to 1080 p at 60 Hz. With any-to-any
color space support, formats such as RGB, YUV, YCbCr, and
others are supported by the CSC.
The main inputs, Rin, Gin, and Bin come from the 8- to 12-bit
inputs from each channel. These inputs are based on the input
format detailed in Table 7 to Table 15. The mapping of these
inputs to the CSC inputs is shown in Table 9.
Table 9. CSC Port Mapping
Input Channel
CSC Input Channel
R/CR
RIN
Gr/Y
GIN
B/CB
B
IN
One of the three channels is represented in Figure 13. In each
processing channel the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
–0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2csc_mode.
The functional diagram for a single channel of the CSC as
shown in Figure 13 is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
05087-
013
×2
2
1
0
×
a1[12:0]
a2[12:0]
a3[12:0]
RIN [11:0]
BIN [11:0]
GIN [11:0]
+
×4
CSC_MODE[1:0]
a4[12:0]
ROUT [11:0]
+
1
4096
×
1
4096
×
1
4096
×
+
Figure 13. Single CSC Channel
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