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| 型号： | EVAL-AD9880-ABZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/64页 |
| 文件大小： | 0K |
| 描述： | KIT MODULE VIDEO INPUT AD9880 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要属性： | HDMI 接收器和模拟接口 |
| 次要属性： | 3 路 8 位 150MSPS ADC |
| 已供物品： | 板 |
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AD9880
Rev. 0 | Page 10 of 64
Pin
Description
PWRDN
Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
FILT
External Filter Connection.
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to
this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the section on
PCB Layout Recommendations.
OUTPUTS
HSOUT
Horizontal Sync Output.
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be
programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.
VSOUT
Vertical Sync Output.
The separated Vsync from a composite signal or a direct pass through of the Vsync signal. The polarity of this output
can be controlled via serial bus bit (Register 0x24 [6]).
SOGOUT
Sync-On-Green Slicer Output.
This pin outputs one of four possible signals (controlled by Register 0x1D [1:0]): raw SOG, raw Hsync, regenerated
Hsync from the filter, or the filtered Hsync. See the Sync processing block diagram (see Figure 8) to view how this pin is
connected. (Note: besides slicing off SOG, the output from this pin is not processed on the AD9880. Vsync separation is
performed via the sync separator.
O/E FIELD
Odd/Even Field Bit for Interlaced Video. This output will identify whether the current field (in an interlaced signal) is odd
or even. The polarity of this signal is programmable via Register 0x24[4].
SERIAL PORT
SDA
Serial Port Data I/O for programming AD9880 registers – I2C address is 0x98.
SCL
Serial Port Data Clock for programming AD9880 registers.
DDCSDA
Serial Port Data I/O for HDCP communications to transmitter – I2C address is 0x74 or 0x76.
DDCSCL
Serial Port Data Clock for HDCP communications to transmitter.
MDA
Serial Port Data I/O to EEPROM with HDCP keys – I2C address is 0xA0
MCL
Serial Port Data Clock to EEPROM with HDCP keys.
DATA OUTPUTS
Red [7:0]
Data Output, Red Channel.
Green [7:0]
Data Output, Green Channel.
Blue [7:0]
Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is
fixed, but will be different if the color space converter is used. When the sampling time is changed by adjusting the
phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
DATA CLOCK
OUTPUT
DATACK
Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output
clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2×
frequency pixel clock and a 90° phase shifted pixel clock) and they are produced either by the internal PLL clock
generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted
via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register.
When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
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