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| 型号： | EVAL-AD9880-ABZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/64页 |
| 文件大小： | 0K |
| 描述： | KIT MODULE VIDEO INPUT AD9880 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要属性： | HDMI 接收器和模拟接口 |
| 次要属性： | 3 路 8 位 150MSPS ADC |
| 已供物品： | 板 |
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AD9880
Rev. 0 | Page 40 of 64
0x13
7-0
Precoast
This register allows the internally generated Coast
signal to be applied prior to the Vsync signal. This is
necessary in cases where pre-equalization pulses are
present. The step size for this control is one Hsync
period. For Precoast to work correctly, it is necessary
for the Vsync filter (0x21, Bit 5) and sync processing
filter (0x21 Bit 7) both to be either enabled or
disabled. The power-up default is 0.
0x14
7-0
Postcoast
This register allows the internally generated Coast
signal to be applied following the Vsync signal. This is
necessary in cases where post-equalization pulses are
present. The step size for this control is one Hsync
period. For Postcoast to work correctly, it is necessary
for the Vsync filter (0x21, Bit 5) and sync processing
filter (0x21, Bit 7) both to be either enabled or
disabled. The power-up default is 0.
STATUS OF DETECTED SIGNALS
0x15
7
Hsync0 Detection Bit
Indicates if Hsync0 is active. This bit is used to
indicate when activity is detected on the Hsync0 input
pin. If Hsync is held high or low, activity is not
detected. The sync processing block diagram shows
where this function is implemented. 0 = Hsync0 not
active. 1 = Hsync0 is active.
Table 15. Hsync0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x15
6
Hsync1 Detection Bit
Indicates if Hsync1 is active. This bit is used to indi-
cate when activity is detected on the Hsync1 input pin.
If Hsync is held high or low, activity is not detected.
The sync processing block diagram shows where this
function is implemented. 0 = Hsync1 not active.
1 = Hsync1 is active.
Table 16. Hsync1 Detection Result
Detect
Result
0
No activity detected
1
Activity detected
0x15
5
Vsync0 Detection Bit
Indicates if Vsync0 is active. This bit is used to
indicate when activity is detected on the Vsync0 input
pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows
where this function is implemented. 0 = Vsync0 not
active. 1 = Vsync0 is active.
Table 17. Vsync0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x15
4
Vsync1 Detection Bit
Indicates if Vsync1 is active. This bit is used to
indicate when activity is detected on the Vsync1 input
pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows
where this function is implemented. 0 = Vsync1 not
active. 1 = Vsync1 is active.
Table 18. Vsync1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x15
3
SOG0 Detection Bit
Indicates if SOG0 is active. This bit is used to indicate
when activity is detected on the SOG0 input pin. If
SOG is held high or low, activity is not detected. The
sync processing block diagram shows where this
function is implemented. 0 = SOG0 not active.
1 = SOG0 is active.
Table 19. SOG0 Detection Result
Detect
Result
0
No activity detected
1
Activity detected
0x15
2
SOG1 Detection Bit
Indicates if SOG1 is active. This bit is used to indicate
when activity is detected on the SOG1 input pin. If
SOG is held high or low, activity is not detected. The
sync processing block diagram shows where this
function is implemented. 0 = SOG1 not active.
1 = SOG1 is active.
Table 20. SOG1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
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