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参数资料
| 型号： | FAN5355UC08X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 17/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 12WLCSP |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 1.4375 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1.1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-WLCSP |
Circuit Description
Overview
The FAN5355 is a synchronous buck regulator that typically
operates at 3MHz with moderate to heavy load currents. At
Power-Up, EN, and Soft-Start
All internal circuits remain de-biased and the IC is in a very
low quiescent-current state until the following are true:
light load currents, the converter operates in power-saving
PFM mode. The regulator automatically transitions between
fixed-frequency PWM and variable-frequency PFM mode to
1.
2.
V IN is above its rising UVLO threshold, and
EN is HIGH.
At that point, the IC begins a soft-start cycle, its I C interface is
maintain the highest possible efficiency over the full range of
load current.
The FAN5355 uses a very fast non-linear control architecture
to achieve excellent transient response with minimum-sized
external components.
The FAN5355 integrates an I 2 C-compatible interface, allowing
transfers up to 3.4Mbps. This communication interface can be
used to:
1. Dynamically re-program the output voltage in 12.5mV
increments.
2. Reprogram the mode of operation to enable or disable
PFM mode.
3. Control voltage transition slew rate.
4. Control the frequency of operation by synchronizing to an
external clock.
2
enabled, and its registers are loaded with their default values.
During the initial soft start, V OUT ramps linearly to the set point
programmed in the VSEL register selected by the VSEL pin.
The soft start features a fixed output-voltage slew rate of
18.75V/ms and achieves regulation approximately 90 ? s after
EN rises. PFM mode is enabled during soft start until the
output is in regulation, regardless of the MODE bit settings.
This allows the regulator to start into a partially charged output
without discharging it; in other words, the regulator does not
allow current to flow from the load back to the battery.
As soon as the output has reached its set point, the control
forces PWM mode for about 85 ? s to allow all internal control
circuits to calibrate.
Symbol Description Value ( ? s)
5. Enable / disable the regulator.
For more details, refer to the I 2 C Interface and Register
Description sections.
Output Voltage Programming
Option (11) V OUT Equation
00, 02, 03, 08 V OUT ? 0 . 75 ? N VSEL ? 12 . 5 mV (1)
t SSDLY
t REG
t POK
Time from EN to start of
soft-start ramp
V OUT ramp Opt 03, 06
start to Opt 00,
regulation 02, 08
PWROK (CONTROL2[5])
rising from end of t REG and
regulator stays in PWM
mode during this time
75
16 +(VSEL–0.7) X 53
(VSEL–0.1) X 53
10
06
V OUT ? 1 . 1875 ? N VSEL ? 12 . 5 mV
(2)
Table 2. Soft-Start Timing (see Figure 37)
where N VSEL is the decimal value of the setting of the VSEL
register that controls V OUT .
Note:
11. Option 02 and 08 maximum voltage is 1.4375V (see
Table 3) .
Figure 37. Soft-Start Timing
? 2008 Fairchild Semiconductor Corporation
FAN5355 ? Rev. 1.1.0
17
www.fairchildsemi.com
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