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| 型号： | FAN5355UC08X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 3/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 12WLCSP |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 1.4375 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1.1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-WLCSP |
Pin Configuration
Top View
Bottom View
Top View
Figure 2. WLCSP-12, 2.23x1.46mm
Pin Definitions
Figure 3. MLP10, 3x3mm
Pin #
WLCSP
MLP
Name (5) Description
A1, B1
A2
A3
9
10
1
PGND
SW
PVIN
Power GND . Power return for gate drive and power transistors. Connect to AGND on PCB.
The connection from this pin to the bottom of C IN should be as short as possible.
Switching Node . Connect to output inductor.
Power Input Voltage . Connect to input power source. The connection from this pin to C IN
should be as short as possible.
Sync . When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency
B2
N/A
SYNC
on this pin. In PWM mode, when this pin is statically LOW or statically HIGH, or when its
frequency is outside of the specified capture range, the regulator’s frequency is controlled by
its internal 3MHz clock.
B3
C1
C2
C3
D1
D2
D3
2
8, PAD
7
3
6
5
4
AVIN
AGND
EN
SDA
VOUT
VSEL
SCL
Analog Input Voltage . Connect to input power source as close as possible to the input
bypass capacitor.
Analog GND . This is the signal ground reference for the IC. All voltage levels are measured
with respect to this pin.
Enable . When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is
minimized. This pin should not be left floating.
SDA . I 2 C interface serial data.
Output Voltage Monitor . Tie this pin to the output voltage. This is a signal input pin to the
control circuit and does not carry DC current.
Voltage Select . When HIGH, V OUT is set by VSEL1. When LOW, V OUT is set by VSEL0. This
behavior can be overridden through I 2 C register settings. This pin should not be left floating.
SCL . I 2 C interface serial clock.
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I C control is unused, tie SDA and SCL to AVIN.
Note:
5. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
2
? 2008 Fairchild Semiconductor Corporation
FAN5355 ? Rev. 1.1.0
3
www.fairchildsemi.com
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