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参数资料
| 型号： | FAN5355UC08X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 19/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 12WLCSP |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 1.4375 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1.1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-WLCSP |
Switching-Frequency Control and
Synchronization
The nominal internal oscillator frequency is 3MHz. The
regulator runs at its internal clock frequency until these
conditions are met:
1. EN_SYNC bit, CONTROL1[5], is set; and
Multi-Step Mode:
Applies to Options 03 and 06 only.
The internal DAC is stepped at a rate defined by DEFSLEW,
CONTROL2[2:0], ranging from 000 to 110. This mode
minimizes the current required to charge C OUT and thereby
minimizes the current drain from the battery when
2. A valid frequency appears on the SYNC pin.
CONTROL2 f SYNC Valid
PLL_MULT f SYNC Divider Min. Typ.
Max.
transitioning. The PWROK bit, CONTROL2[5], remains LOW
until about 1.5 ? s after the DAC completes its ramp.
VHIGH
00
01
1
2
1.80
0.90
3.00
1.50
4.00
2.00
10
11
3
4
0.60
0.45
1.00
0.75
1.33
1.00
VOUT
VLOW
Table 5. SYNC Frequency Validation for f OSC(INTERNAL) =3.0MHz
VSEL
If the EN_SYNC is set and SYNC fails validation, the regulator
continues to run at its internal oscillator frequency. The
PWROK
t POK(L-H)
regulator is functional if f SYNC is valid, as defined in Table 5,
but its performance is compromised if f SYNC is outside the f SYNC
window in the Electrical Specifications.
When CONTROL1[3:2] = 00 and the VSEL line is LOW, the
converter operates according to the MODE0 bit,
CONTROL1[0], with synchronization disabled regardless of
the state of the EN_SYNC and HW_nSW bits.
Output Voltage Transitions
The IC regulates V OUT to one of two set point voltages, as
determined by the VSEL pin and the HW_nSW bit.
VSEL Pin HW_nSW Bit V OUT Set Point PFM
Figure 38. Multi-Step V OUT Transition
Single-Step Mode:
Used if DEFSLEW, CONTROL2[2:0] = 111. The internal DAC
is immediately set to the higher voltage and the regulator
performs the transition as quickly as its current-limit circuit
allows, while avoiding excessive overshoot.
Figure 39 shows single-step transition timing. t V(L-H) is the time
it takes the regulator to settle to within 2% of the new set point
and is typically 7 ? s for a full-range transition (from 000000 to
111111). The PWROK bit, CONTROL2[5], goes LOW until the
transition is complete and V OUT settled. This typically occurs
~2 ? s after t V(L-H) .
0
1
x
1
1
0
VSEL0
VSEL1
VSEL1
Allowed
Per MODE1
Per MODE1
It is good practice to reduce the load current before making
positive VSEL transitions. This reduces the time required to
make positive load transitions and avoids current-limit-induced
Table 6. V OUT Set Point and Mode Control MODE_CTRL,
CONTROL1[3:2] = 00
If HW_nSW = 0, V OUT transitions are initiated through the
following sequence:
overshoot.
VHIGH
t V(L-H)
98% VHIGH
1. Write the new setpoint in VSEL1.
2. Write desired transition rate in DEFSLEW,
CONTROL2[2:0], and set the GO bit in CONTROL2[7].
VOUT
VLOW
If HW_nSW = 1, V OUT transitions are initiated either by
changing the state of the VSEL pin or by writing to the VSEL
register selected by the VSEL pin.
VSEL
PWROK
t POK(L-H)
Positive Transitions
When transitioning to a higher V OUT , the regulator can perform
the transition using multi-step or single-step mode.
Figure 39. Single-Step V OUT Transition
All positive V OUT transitions inhibit PFM until the transition is
complete, which occurs at the end of t POK(L-H) .
? 2008 Fairchild Semiconductor Corporation
FAN5355 ? Rev. 1.1.0
19
www.fairchildsemi.com
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