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参数资料
| 型号： | FAN5355UC08X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 23/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 12WLCSP |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 1.4375 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1.1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-WLCSP |
signify the default values for options 00, 02, 03, 06, and 08 respectively. A signifies the default for all options.
Superscripts
Bit Definitions
The following table defines the operation of each register bit. Superscript characters define the default state for each option.
0,2,3,6,8
Bit Name
VSEL0
Value Description
Register Address: 00
1
7
6
5:0
EN_DCDC
Reserved
DAC[5:0]
0
A
1
Table
10
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either
register establishes the EN_DCDC value.
Device enabled when EN pin is HIGH, disabled when EN is LOW.
6-bit DAC value to set V OUT .
VSEL1
Register Address: 01
1
7
6
5:0
EN_DCDC
Reserved
DAC[5:0]
0
A
1
Table
10
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL0. A write to bit 7 in either
register establishes the EN_DCDC value.
Device enabled when EN pin is HIGH, disabled when EN is LOW.
6-bit DAC value to set V OUT .
CONTROL1
Register Address: 02
between vendors via I C.
7:6
Reserved
10
A
Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be used to distinguish
2
0
A
Disables external signal on SYNC from affecting the regulator.
1
5
4
EN_SYNC
HW_nSW
1
0
A
A
00
When a valid frequency is detected on SYNC, the regulator synchronizes to it and PFM is disabled, except
when MODE = 00, VSEL pin = LOW, and HW_nSW = 1.
V OUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit.
V OUT is programmed by the VSEL pin. V OUT = VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW.
Operation follows MODE0, MODE1.
3:2 MODE_CTRL
01
10
11
PFM with automatic transitions to PWM, regardless of VSEL.
PFM disabled (forced PWM), regardless of VSEL.
Unused.
0
0
1
0
MODE1
MODE0
A
1
A
1
PFM disabled (forced PWM) when regulator output is controlled by VSEL1.
PFM with automatic transitions to PWM when regulator output is controlled by VSEL1.
PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the operation of
the regulator.
CONTROL2
Register Address: 03
0
A
This bit has no effect when HW_nSW = 1.
0
7
6
5
4:3
2:0
GO
OUTPUT_
DISCHARGE
PWROK
(read only)
PLL_MULT
DEFSLEW
1
A
1
0
1
A
00
01
10
11
000
001
010
011
100
101
110
A
111
Starts a V OUT transition if HW_nSW = 0. This bit must be written by the external master to 1 for the next V OUT
transition to start, even if its value might have already been 1 from the last V OUT transition.
When the regulator is disabled, V OUT is not discharged.
When the regulator is disabled, V OUT discharges through an internal pull down.
V OUT is not in regulation or is in current limit.
V OUT is in regulation.
f SW = f SYNC when synchronization is enabled.
f SW = 2 X f SYNC when synchronization is enabled.
f SW = 3 X f SYNC when synchronization is enabled.
f SW = 4 X f SYNC when synchronization is enabled.
V OUT slews at 0.15mV/ ? s during positive V OUT transitions.
V OUT slews at 0.30mV/ ? s during positive V OUT transitions.
V OUT slews at 0.60mV/ ? s during positive V OUT transitions.
V OUT slews at 1.20mV/ ? s during positive V OUT transitions.
V OUT slews at 2.40mV/ ? s during positive V OUT transitions.
V OUT slews at 4.80mV/ ? s during positive V OUT transitions.
V OUT slews at 9.60mV/ ? s during positive V OUT transitions.
Positive V OUT transitions use single-step mode (see Figure 39) .
? 2008 Fairchild Semiconductor Corporation
FAN5355 ? Rev. 1.1.0
23
www.fairchildsemi.com
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