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参数资料
| 型号： | FAN5355UC08X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 20/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 12WLCSP |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 1.4375 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1.1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-WLCSP |
Negative Transitions
When moving from VSEL=1 to VSEL=0, the regulator enters
PFM mode, regardless of the condition of the SYNC pin or
MODE bits, and remains in PFM until the transition is
completed. Reverse current through the inductor is blocked,
and the PFM minimum frequency control inhibited, until the
new set point is reached, at which time the regulator resumes
control using the mode established by MODE_CTRL. The
transition time from V HIGH to V LOW is controlled by the load
current and output capacitance as:
I 2 C Interface
The FAN5355’s serial interface is compatible with standard,
fast, and HS mode I 2 C bus specifications. The FAN5355’s
SCL line is an input and its SDA line is a bi-directional open-
drain output; it can only pull down the bus when active. The
SDA line only pulls LOW during data reads and when
signaling ACK. All data is shifted in MSB (bit 7) first.
SDA and SCL are normally pulled up to a system I/O power
supply (VCCIO), as shown in Figure 1. If the I 2 C interface is
t V ( H ? L ) ? C OUT ?
V HIGH ? V LOW
I LOAD
(3)
not used, SDA and SCL should be tied to AVIN to minimize
quiescent current consumption.
Addressing
VHIGH
FAN5355 has four user-accessible registers:
Address
VOUT
VLOW
t V(L-H)
VSEL
t POK(L-H)
PWROK
Figure 40. Negative V OUT Transition
7 6 5
VSEL0 0 0 0
VSEL1 0 0 0
CONTROL1 0 0 0
CONTROL2 0 0 0
Table 7. I 2 C Register Addresses
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
Slave Address
Protection Features
Current Limit / Auto-Restart
In Table 8, A1 and A0 are according to the Ordering
Information table on page 2.
The regulator includes cycle-by-cycle current limiting, which
prevents the instantaneous inductor current from exceeding
the current-limit threshold.
7
1
6
0
5
0
4
1
3
0
2
A1
1
A0
0
R/ W
The IC enters “fault” mode after sustained over-current. If
Table 8.
I 2 C Slave Address
current limit is asserted for more than 32 consecutive cycles
(about 20 ? s), the IC returns to shut-down state and remains in
that condition for ~80 ? s. After that time, the regulator attempts
to restart with a normal soft-start cycle. If the fault has not
cleared, it shuts down ~10 ? s later.
If the fault is a short circuit, the initial current limit is ~30% of
the normal current limit, which produces a very small drain on
the system power source.
Thermal Protection
When the junction temperature of the IC exceeds 150°C, the
device turns off all output MOSFETs and remains in a low
quiescent-current state until the die cools to 130°C before
Bus Timing
As shown in Figure 41, data is normally transferred when SCL
is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge of
SCL to allow ample time for the data to set up before the next
SCL rising edge.
Data change allowed
SDA
T H
commencing a normal soft-start cycle.
SCL
T SU
Under-Voltage Lockout (UVLO)
The IC turns off all MOSFETs and remains in a very low
quiescent-current state until V IN rises above the UVLO
threshold.
Figure 41. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a “START” condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 42.
? 2008 Fairchild Semiconductor Corporation
FAN5355 ? Rev. 1.1.0
20
www.fairchildsemi.com
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