参数资料
型号: FDC3535
厂商: Fairchild Semiconductor
文件页数: 2/7页
文件大小: 0K
描述: MOSFET P-CH 80V 6-SSOT
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET P 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 80V
电流 - 连续漏极(Id) @ 25° C: 2.1A
开态Rds(最大)@ Id, Vgs @ 25° C: 183 毫欧 @ 2.1A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 20nC @ 10V
输入电容 (Ciss) @ Vds: 880pF @ 40V
功率 - 最大: 700mW
安装类型: 表面贴装
封装/外壳: SOT-23-6 细型,TSOT-23-6
供应商设备封装: 6-SSOT
包装: 标准包装
其它名称: FDC3535DKR
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DSS
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0 V
I D = -250 μ A, referenced to 25 °C
V DS = -64 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
-80
-64
-1
±100
V
mV/°C
μ A
nA
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 μ A
I D = -250 μ A, referenced to 25 °C
-1
-1.6
5
-3
V
mV/°C
V GS = -10 V, I D = -2.1 A
147
183
r DS(on)
Static Drain to Source On Resistance
V GS = -4.5 V, I D = -1.9 A
176
233
m Ω
V GS = -10 V, I D = -2.1 A, T J = 125 °C
246
307
g FS
Forward Transconductance
V DD = -10 V, I D = -2.1 A
6.3
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = -40 V, V GS = 0 V,
f = 1 MHz
659
49
24
5.7
880
65
40
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
6.5
13
ns
t r
t d(off)
t f
Q g(TOT)
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
V DD = -40 V, I D = -2.1 A,
V GS = -10 V, R GEN = 6 Ω
V GS = 0 V to -10 V
V GS = 0 V to -4.5 V V DD = -40 V
I D = -2.1 A
3.1
23
2.9
14
6.8
1.6
2.7
10
38
10
20
10
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = -2.1 A
I F = -2.1 A, di/dt = 100 A/ μ s
(Note 2)
-0.81
25
23
-1.3
40
38
V
ns
nC
NOTES:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
a. 78 °C/W when mounted on
a 1 in 2 pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0 %.
3. Starting T J = 25 o C, L = 3 mH, I AS = -5 A, V DD = -80 V, V GS = -10 V.
b.175 °C/W when mounted on
a minimum pad of 2 oz copper
?2010 Fairchild Semiconductor Corporation
FDC3535 Rev. C
2
www.fairchildsemi.com
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