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参数资料
| 型号： | FDD14AN06LA0_F085 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 60V 9.5A DPAK-3 |
| 标准包装： | 2,500 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 60V |
| 电流 - 连续漏极(Id) @ 25° C： | 9.5A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 11.6 毫欧 @ 50A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 32nC @ 5V |
| 输入电容 (Ciss) @ Vds： | 2810pF @ 25V |
| 功率 - 最大： | 125W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252 |
| 包装： | 带卷 (TR) |
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T JM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P DM , in an
application. Therefore the application’s ambient
temperature, T A ( o C), and thermal resistance R θ JA ( o C/W)
must be reviewed to ensure that T JM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
125
100
75
R θ JA = 33.32+ 23.84/(0.268+Area) EQ.2
R θ JA = 33.32+ 154/(1.73+Area) EQ.3
( T – T )
R θ JA
JM A
P D M = -----------------------------
(EQ. 1)
50
In using surface mount devices such as the TO-252
25
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
0.01
(0.0645)
0.1
(0.645)
1
(6.45)
10
(64.5)
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer ’s preliminary application evaluation. Figure 21
defines the R θ JA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
AREA, TOP COPPER AREA in 2 (cm 2 )
Figure 21. Thermal Resistance vs Mounting
Pad Area
( 0.268 + Area )
R
θ JA
23.84
= 33.32 + -------------------------------------
(EQ. 2)
Area in Inches Squared
( 1.73 + Area )
R
θ JA
154
= 33.32 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
?2010 Fairchild Semiconductor Corporation
FDD14AN06LA0_F085 Rev. C
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