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参数资料
| 型号： | FDD4685_F085 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 40V 8.4A DPAK |
| 标准包装： | 2,500 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 40V |
| 电流 - 连续漏极(Id) @ 25° C： | 32A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 27 毫欧 @ 8.4A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 27nC @ 5V |
| 输入电容 (Ciss) @ Vds： | 2380pF @ 20V |
| 功率 - 最大： | 83W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252 |
| 包装： | 带卷 (TR) |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DS S
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = –250 μ A, V GS = 0V
I D = –250 μ A, referenced to 25°C
V DS = –32V, V GS = 0V
V GS = ±20V, V GS = 0V
–40
–33
–1
±100
V
mV/° C
μ A
nA
On Characteristics (Note 2)
V GS(th)
? V GS(th )
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = –250 μ A
I D = –250 μ A, referenced to 25°C
–1
–1.6
4.9
–3
V
mV/°C
V GS = –10V, I D = –8.4A
23
27
r DS(on)
Static Drain to Source On Resistance
V GS = –4.5V, I D = –7A
30
35
m ?
V GS = –10V, I D = –8.4A, T J =125°C
33
42
g FS
Forward Transconductance
V DS = –5V, I D = –8.4A
23
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = –20V, V GS = 0V,
f = 1MHz
f = 1MHz
1790
260
140
4
2380
345
205
pF
pF
pF
?
Switching Characteristics
t d(on)
t r
t d(off)
t f
Q g(TOT)
Q gs
Q gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V DD = –20V, I D = –8.4A
V GS = –10V, R GEN = 6 ?
V DD =–20V, I D = –8.4A
V GS = –5V
8
15
34
14
19
5.6
6.1
16
27
55
26
27
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0V, I S = –8.4A
(Note 2)
–0.85
–1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = –8.4A, di/dt = 100A/ μ s
30
31
45
47
ns
nC
Notes:
1: R θ JA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user ’s board design.
a. 40°C/W when mounted on a 1 in 2 pad of 2 oz copper
b. 96°C/W when mounted on a minimum pad.
2: Pulse Test: Pulse Width < 30 0 μ s, Duty cycle < 2.0%.
3: Starting T J = 25°C, L = 3mH, I AS = 9A, V DD = 40V, V GS = 10V.
FDD4685 Rev.B
2
www.fairchildsemi.com
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