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| 型号： | FDG6335N |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 20V 700MA SOT-363 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 Mold Compound Change 07/May/2008 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | 2 个 N 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 700mA |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 300 毫欧 @ 700mA，4.5V |
| Id 时的 Vgs(th)（最大）： | 1.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 1.4nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 113pF @ 10V |
| 功率 - 最大： | 300mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 标准包装 |
| 其它名称： | FDG6335NDKR |
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Off Characteristics
BV DSS
Drain–Source Breakdown
V GS = 0 V,
I D = 250 μ A
20
V
Voltage
? BV DSS
? T J
Breakdown Voltage Temperature
Coefficient
I D = 250 μ A, Referenced to 25 ° C
14
mV/ ° C
I DSS
I GSSF
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
V DS = 16 V,
V GS = 12 V,
V GS = 0 V
V DS = 0 V
1
100
μ A
nA
I GSSR
Gate–Body Leakage, Reverse
V GS = –12 V, V DS = 0 V
–100
nA
On Characteristics
(Note 2)
V GS(th)
Gate Threshold Voltage
V DS = V GS ,
I D = 250 μ A
0.6
1.1
1.5
V
? V GS(th)
? T J
Gate Threshold Voltage
Temperature Coefficient
I D = –250 μ A, Referenced to 25 ° C
–2.8
mV/ ° C
R DS(on)
Static Drain–Source
On–Resistance
V GS = 4.5 V,
V GS = 2.5 V,
I D = 0.7 A
I D = 0.6 A
180
293
300
400
m ?
V GS = 4.5 V,
I D = 0.7 A, T J =125°C
247
442
I D(on)
g FS
On–State Drain Current
Forward Transconductance
V GS = 4.5 V,
V DS = 5 V,
V DS = 5 V
I D = 0.7 A
1
2.8
A
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = 10 V,
f = 1.0 MHz
V GS = 0 V,
113
34
16
pF
pF
pF
Switching Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
V DD = 10 V, I D = 1 A,
V GS = 4.5 V, R GEN = 6 ?
5
7
9
1.5
10
15
18
3
ns
ns
ns
ns
Q g
Q gs
Total Gate Charge
Gate–Source Charge
V DS = 10 V,
V GS = 4.5 V
I D = 0.7 A,
1.1
0.24
1.4
nC
nC
Q gd
Gate–Drain Charge
0.3
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
0.25
A
V SD
Drain–Source Diode Forward
V GS = 0 V,
I S = 0.25 A
(Note 2)
0.74
1.2
V
Voltage
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ JA is determined by the user's board design. R θ JA = 415°C/W when mounted on a minimum pad .
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
FDG6335N Rev C (W)
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